IMX51-Spartan6 interface description - Revision history

FabienM: /* Chip Select */

2021-09-07T15:14:38Z

‎Chip Select

2021-09-07T14:45:51Z

‎Chip Select

2020-08-03T12:26:24Z

‎FPGA side

2020-08-03T12:23:48Z

‎FPGA side

2020-08-03T12:23:33Z

‎The FPGA interrupt

2019-03-19T14:57:04Z

2015-02-12T07:32:12Z

2014-07-09T14:18:21Z

‎Default configuration on CS1

2013-10-03T13:21:37Z

‎Clock

2013-10-03T13:09:23Z

‎Clock: hum ...

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 It's possible to use the second chip select (CS2) to extend memory domain or to use different timing configuration with the same Address/Data bus signals.
 The default bus configuration for the APF51 can be found in the file apf51.h in u-boot sources :
 ''buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h''
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 #define	CONFIG_FPGA_WCR1_VALUE	0x04000008
 #define	CONFIG_FPGA_WCR2_VALUE	0x00000000
 </source>
 {{Note| Do not forget to do :
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 To access these register with U-Boot or Linux, use the address given under the reference manual in WEIM register descriptions (63.4.3 Register Descriptions).
 {{Note| The 0xBASE value is given in chapter 2 "Memory Map" (page 65) : 0xBASE -> 0x83FD8000}}
 ==== Timings ====

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 === Chip Select ===
-By default the chip select 1 (CS1) is used for communication. The address domain corresponding to this chip select can be found in i.MX51 reference manual in chapter 2 (Memory Map page 65).
+By default the chip select 1 (CS1) is used for communication. The address domain corresponding to this chip select can be found in [https://www.nxp.com/docs/en/reference-manual/MCIMX51RM.pdf i.MX51 reference manual] in chapter 2 (Memory Map page 65).
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 === FPGA side ===
-By default, the wishbone bus is used under the spartan6 fpga. Then a WEIM to Wishbone wrapper is used, this wrapper is available under [https://github.com/Martoni/periphondemand POD] default libraries in ''wrappers'' lib. The component is named ''imx51_wb16_wrapper''.
+By default, the wishbone bus is used under the spartan6 fpga. Then a WEIM to Wishbone wrapper is used, this wrapper is available under [https://github.com/Martoni/pod_lib/tree/master/platforms/apf51 POD] default libraries in ''wrappers'' lib. The component is named ''imx51_wb16_wrapper''.
 == The FPGA interrupt ==

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 === FPGA side ===
-By default, the wishbone bus is used under the spartan6 fpga. Then a WEIM to Wishbone wrapper is used, this wrapper is available under [http://periphondemand.sourceforge.net/ POD] default libraries in ''wrappers'' lib. The component is named ''imx51_wb16_wrapper''.
+By default, the wishbone bus is used under the spartan6 fpga. Then a WEIM to Wishbone wrapper is used, this wrapper is available under [https://github.com/Martoni/periphondemand POD] default libraries in ''wrappers'' lib. The component is named ''imx51_wb16_wrapper''.
 == The FPGA interrupt ==

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 == The FPGA interrupt ==
-By default under [http://periphondemand.sourceforge.net/ POD] the pin '''FPGA_INITB''' (gpio4_11) is used for the interrupts manager ''irq_mngr''. For simple user application the gpio can be used with the [[GPIOlib]] interface, the gpio number will then be (4-1)x32+11 = '''107'''.
+By default under [https://github.com/Martoni/periphondemand POD] the pin '''FPGA_INITB''' (gpio4_11) is used for the interrupts manager ''irq_mngr''. For simple user application the gpio can be used with the [[GPIOlib]] interface, the gpio number will then be (4-1)x32+11 = '''107'''.
 == Links ==
 * [http://billauer.co.il/blog/2011/10/imx51-imx-weim-freescale-arm-bus/ Eli Billauer investigation].

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 [[Category: APF51]]
 [[Category: FPGA]]
 == Introduction ==

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 === Clock ===
-The clock used to clock the fpga is ''BCLK'' and is configured to '''95 MHz'''.
+The clock used to clock the fpga is ''BCLK'' (IO_L29P_GCLK3_2 on Spartan6) and is configured to '''95 MHz'''.
 === Chip Select ===