IMX6-CycloneV interface description - Revision history

JulienB: /* Links */

2017-08-07T12:44:48Z

‎Links

2016-03-21T14:01:10Z

‎Clocking without PCIe

2016-03-21T14:00:56Z

‎Clocking without PCIe

2016-03-21T12:55:43Z

2016-02-02T16:45:31Z

‎FPGA pinout

2016-02-02T16:43:01Z

‎FPGA pinout

2016-02-02T16:42:06Z

‎FPGA pinout

2016-01-14T10:59:07Z

‎Avalon-MM Cyclone V Hard IP for PCI Express

2016-01-14T10:47:08Z

‎Simplified view

2015-08-26T06:41:13Z

‎Qsys (Quartus) : Avalon-MM Cyclone V Hard IP for PCI Express configuration (CvP)

@@ Line 173: / Line 173: @@
 == Links ==
-=== In this wiki ===
+* [[pci_debug | '''pci_debug''': a useful commands tool to access PCIe BARx]]
-* [[pci_debug | '''pci_debug''': a usefull commands tool to access PCIe BARx]]
-−
-=== External ===
-−
 * [http://www.altera.com/literature/ug/ug_c5_pcie_avmm.pdf Avalon-MM to PCIe interface for CycloneV]

← Older revision		Revision as of 14:01, 21 March 2016
Line 170:		Line 170:


−	A blinking led example is provided in BSP under the directory '''firmware/leds/blinking_led/src/cycloneV'''.	+	A blinking led example is provided in BSP under the directory '''firmware/leds/blinking_led/src/cycloneV/'''.

	== Links ==		== Links ==

@@ Line 170: / Line 170: @@
- {{Under_Construction}}
+A blinking led example is provided in BSP under the directory '''firmware/leds/blinking_led/src/cycloneV'''.
 == Links ==
 === In this wiki ===

@@ Line 166: / Line 166: @@
 PCIe_clk input can be used to clock the entire design without using the PCIe hard ip-core. But it can't be use directly, PLL must be instancied.
   {{Under_Construction}}
 == Links ==

@@ Line 160: / Line 160: @@
 === FPGA pinout ===
-<pre>
+FPGA pinout is the [[APF6_SP_DDR3_PINOUT#PCIe | following]]
-# PCIE_RX
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hip_serial_rx_in0
-set_location_assignment PIN_AA2 -to hip_serial_rx_in0
-set_location_assignment PIN_AA1 -to "hip_serial_rx_in0(n)"
-# PCIE_TX
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hip_serial_tx_out0
-set_location_assignment PIN_Y4 -to hip_serial_tx_out0
-set_location_assignment PIN_Y3 -to "hip_serial_tx_out0(n)"
-# PCIE_CLK
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to refclk_clk
-set_location_assignment PIN_V4 -to refclk_clk
-set_location_assignment PIN_U4 -to "refclk_clk(n)"
-−
-# nperst
-set_location_assignment PIN_R17 -to nperst
-# npor
-set_location_assignment PIN_R16 -to npor
-</pre>
 == Clocking without PCIe ==

@@ Line 161: / Line 161: @@
 === FPGA pinout ===
 FPGA pinout is the following :
-[[File:pcie_pinout.tcl]]
 <pre>
 # PCIE_RX

@@ Line 42: / Line 42: @@
 * Number of lanes : '''x1'''
 * Reference clock frequency : '''125Mhz'''
-* Enable configuration via the PCIe link
+* check "Enable configuration via the PCIe link"
 * BAR0
 ** Type: 32-bit non-prefetchable memory

@@ Line 24: / Line 24: @@
 * '''nperst''': set to vcc.
-* '''coreclkout''': '''125Mhz''' (by default) clock generated by quartus hard PCIe ip-core, used to clock design by defaut.
+* '''coreclkout''': '''62.5Mhz''' (by default) clock generated by quartus hard PCIe ip-core, used to clock design by defaut.
 === Qsys (Quartus 14.0) : Avalon-MM Cyclone V Hard IP for PCI Express configuration (CvP)===

@@ Line 26: / Line 26: @@
 * '''coreclkout''': '''125Mhz''' (by default) clock generated by quartus hard PCIe ip-core, used to clock design by defaut.
-=== Qsys (Quartus) : Avalon-MM Cyclone V Hard IP for PCI Express configuration (CvP)===
+=== Qsys (Quartus 14.0) : Avalon-MM Cyclone V Hard IP for PCI Express configuration (CvP)===
 {{Note| The example project described above can be downloaded [http://www.armadeus.com/_downloads/apf6_SP/hardware/apf6_sp_cvp_example.zip here].}}