IR Receiver - Revision history

JulienB: /* Hardware */

2008-10-29T18:02:43Z

‎Hardware

JulienB: Add fifo register

2008-10-29T18:01:30Z

Add fifo register

JulienB: Add ctrl register

2008-10-29T17:56:21Z

Add ctrl register

JulienB: /* Hardware */

2008-10-29T17:48:24Z

‎Hardware

Salocin68 at 09:29, 29 March 2008

2008-03-29T09:29:48Z

Salocin68 at 09:22, 29 March 2008

2008-03-29T09:22:00Z

JulienB at 15:16, 5 August 2007

2007-08-05T15:16:02Z

JulienB: /* Links */

2007-06-05T20:37:10Z

‎Links

JulienB: page creation

2007-05-03T22:13:11Z

page creation

New page

This page will summarize the informations to connect an InfraRed receiver to your Armadeus board

==Links==
* http://www.positron-libre.com/electronique/protocole/rc5/code-rc5.htm
* http://www.lirc.org/#top

@@ Line 12: / Line 12: @@
 RC5 IP in the FPGA will decode Manchester frames and store them in a FIFO. At that time it will generate an interrupt to signal i.MXL Linux driver that data are available.
-IP will be configurable with:
+This IP will conform to Wishbone/POD interface and be configurable with:
 * a control register to activate/deactivate interrupt
 {| border="0" cellpadding="5" cellspacing="0" summary="IR CTRL"

@@ Line 31: / Line 31: @@
 |}
-* a status register to see interrupt status and acknowledge them
+* a status register to see interrupt status and acknowledge them: will use wishbone irq_handler
-* a FIFO register to get RC5 frame one at a time (and prevent frame lost when one is currently being received)
+* a FIFO register to get RC5 frame one at a time (and prevent frame lost when one is currently being received):
 ==Software==

@@ Line 13: / Line 13: @@
 IP will be configurable with:
-* a configuration register to activate/deactivate interrupt
+* a control register to activate/deactivate interrupt
 * a status register to see interrupt status and acknowledge them
 * a FIFO register to get RC5 frame one at a time (and prevent frame lost when one is currently being received)

@@ Line 6: / Line 6: @@
 ==Hardware==
-For first tries we choose the Sharp's xxxxx as IR receiver. This chip is is 3,3v compatible and can be directly connected to i.MXL or FPGA IOs.
+For our first tries we choose the Sharp's xxxxx IR receiver. This chip is 3,3v compatible and can be directly connected to i.MXL or FPGA IOs.
 As RC5 decoding in software is quite a big overhead, we choose to implement an RC5 decoding IP for the FPGA.<br>
-On x86 architecture a serial port is often used to decode RC5 frame but it's very CPU consumming.
+On x86 architecture a serial port is often used to decode RC5 frames but it's very CPU consuming.
 IP will be configurable with:
-* an configuration register to activate/deactivate interrupt
+* a configuration register to activate/deactivate interrupt
 * a status register to see interrupt status and acknowledge them
-* a FIFO register to get RC5 frame one at a time
+* a FIFO register to get RC5 frame one at a time (and prevent frame lost when one is currently being received)
 ==Software==

← Older revision		Revision as of 09:29, 29 March 2008
Line 25:		Line 25:
	* http://users.pandora.be/davshomepage/rc5.htm		* http://users.pandora.be/davshomepage/rc5.htm

−	[[Category~~:Hardware~~:UserInput]]	+	[[Category:UserInput]]

← Older revision		Revision as of 09:22, 29 March 2008
Line 24:		Line 24:
	* http://www.lirc.org/#top		* http://www.lirc.org/#top
	* http://users.pandora.be/davshomepage/rc5.htm		* http://users.pandora.be/davshomepage/rc5.htm
		+
		+	[[Category:Hardware:UserInput]]

← Older revision		Revision as of 15:16, 5 August 2007
Line 1:		Line 1:
	This page will summarize the informations to connect an InfraRed receiver to your Armadeus board		This page will summarize the informations to connect an InfraRed receiver to your Armadeus board
		+
		+	==Introduction==
		+	Most IR remote control send their key code using the RC5 protocol (see links). This protocol can be mostly seen as a one wire serial Manchester link.
		+	In this application we will see how to user 38Khz carrier IR receiver.
		+
		+	==Hardware==
		+	For first tries we choose the Sharp's xxxxx as IR receiver. This chip is is 3,3v compatible and can be directly connected to i.MXL or FPGA IOs.
		+	As RC5 decoding in software is quite a big overhead, we choose to implement an RC5 decoding IP for the FPGA.<br>
		+	On x86 architecture a serial port is often used to decode RC5 frame but it's very CPU consumming.
		+
		+	RC5 IP in the FPGA will decode Manchester frame and store it in a FIFO. When there are frame in the FIFO the FPGA will generate an interrupt to signal i.MXL Linux driver that data are available
		+	IP will be configurable with:
		+	* an configuration register to activate/deactivate interrupt
		+	* a status register to see interrupt status and acknowledge them
		+	* a FIFO register to get RC5 frame one at a time
		+
		+	==Software==
		+	We will use LIRC framework. A custom Linux driver will have to be written.
		+	As RC5 is very similar to PS/2 we will reuse the work done for PS/2 controller.

	==Links==		==Links==

← Older revision		Revision as of 20:37, 5 June 2007
Line 4:		Line 4:
	* http://www.positron-libre.com/electronique/protocole/rc5/code-rc5.htm		* http://www.positron-libre.com/electronique/protocole/rc5/code-rc5.htm
	* http://www.lirc.org/#top		* http://www.lirc.org/#top
		+	* http://users.pandora.be/davshomepage/rc5.htm