Simple blinking LED - Revision history

FabienM: /* Quartus */

2021-11-25T13:24:02Z

‎Quartus

FabienM: /* Quartus */

2021-11-05T12:57:33Z

‎Quartus

FabienM: /* Quartus */

2021-11-05T12:56:52Z

‎Quartus

FabienM: /* VHDL code */ invert reset

2015-02-18T13:17:18Z

‎VHDL code: invert reset

FabienM: /* VHDL code */

2015-02-17T09:46:08Z

‎VHDL code

FabienM at 09:44, 17 February 2015

2015-02-17T09:44:51Z

FabienM: /* VHDL code */

2015-02-16T13:08:15Z

‎VHDL code

FabienM: /* Pinout */

2015-02-16T09:04:54Z

‎Pinout

FabienM: /* Pinout */

2015-02-16T09:04:26Z

‎Pinout

FabienM at 09:03, 16 February 2015

2015-02-16T09:03:16Z

@@ Line 106: / Line 106: @@
 === Quartus ===
-Se the [[Quartus]] page for tutorials.
+See the [[Quartus]] page for tutorials.
 == Configure FPGA ==

@@ Line 106: / Line 106: @@
 === Quartus ===
-Se the [[Quartus]] page for installation tutorials.
+Se the [[Quartus]] page for tutorials.
 == Configure FPGA ==

@@ Line 106: / Line 106: @@
 === Quartus ===
-{{Under_Construction}}
+Se the [[Quartus]] page for installation tutorials.
 == Configure FPGA ==

@@ Line 21: / Line 21: @@
   architecture RTL of led is
      constant max_count : natural := 48000000;
-     signal Rst_n : std_logic;
+     signal Rst : std_logic;
   begin
-     Rst_n <= '1';
+     Rst <= '0';
      -- 0 to max_count counter
-     compteur : process(refclk, Rst_n)
+     compteur : process(refclk, Rst)
          variable count : natural range 0 to max_count;
      begin
-         if Rst_n = '0' then
+         if Rst = '1' then
              count := 0;
              led <= '1';

@@ Line 21: / Line 21: @@
   architecture RTL of led is
      constant max_count : natural := 48000000;
+    signal Rst_n : std_logic;
   begin

@@ Line 12: / Line 12: @@
   use IEEE.numeric_std.all;
-  entity Clk_div_led is
+  entity led is
      Port (
-            Clk : in  std_logic;
+            refclk : in  std_logic;
             led : out std_logic
      );
-  end Clk_div_led;
+  end led;
-  architecture RTL of Clk_div_led is
+  architecture RTL of led is
-   constant max_count : natural := 48000000;
+    constant max_count : natural := 48000000;
-   signal Rst_n : std_logic;
   begin
-−
      Rst_n <= '1';
      -- 0 to max_count counter
-     compteur : process(Clk, Rst_n)
+     compteur : process(refclk, Rst_n)
          variable count : natural range 0 to max_count;
      begin
          if Rst_n = '0' then
              count := 0;
-         elsif rising_edge(Clk) then
+            led <= '1';
              if count < max_count/2 then
                  count := count + 1;
              elsif count < max_count then
                  count := count + 1;
              else
                  count := 0;
              end if;
@@ Line 47: / Line 50: @@
 === Pinout ===
-To synthesize this code, create a new project and add this VHDL module.
+{{Note| Don't forget to power the FPGA IO bank as explained in [[datasheet]]}}
-−
-{{Note| For '''APF27''' and '''APF51''' don't forget to power the FPGA IO bank as explained in [[datasheet]]}}
 ISE/Quartus need to know where to branch LED pins on its IO, this pinout is describe in constraint file with extension '''.ucf'''.

@@ Line 15: / Line 15: @@
      Port (
             Clk : in  std_logic;
-            led : out std_logic;
+            led : out std_logic
      );
   end Clk_div_led;
@@ Line 45: / Line 45: @@
   end RTL;
 </source>
 === Pinout ===

@@ Line 1: / Line 1: @@
 [[Category: FPGA]]
 This design introduce FPGA usage on APF. The design will allow you to synthesize a design and configure the FGPA to blink a LED.
 == The design ==
@@ Line 20: / Line 14: @@
   entity Clk_div_led is
      Port (
-            Clk             : in  std_logic;
+            Clk : in  std_logic;
-            led_cathode     : out std_logic;
+            led : out std_logic;
-           led_anode       : out std_logic
      );
   end Clk_div_led;
@@ Line 32: / Line 25: @@
      Rst_n <= '1';
-     led_cathode <= '0';
+     led <= '0';
      -- 0 to max_count counter
@@ Line 40: / Line 33: @@
          if Rst_n = '0' then
              count := 0;
          elsif rising_edge(Clk) then
              if count < max_count/2 then
                  count := count + 1;
              elsif count < max_count then
                  count := count + 1;
              else
                  count := 0;
              end if;
          end if;
@@ Line 61: / Line 50: @@
 {{Note| Don't forget to power the FPGA IO bank as explained in [[datasheet]]}}
-ISE need to know where to branch LED pins on its IO, this pinout is describe in constraint file with extension '''.ucf'''.
+ISE/Quartus need to know where to branch LED pins on its IO, this pinout is describe in constraint file with extension '''.ucf'''.
 * For '''APF9328''':
@@ Line 70: / Line 59: @@
 TIMESPEC "TS_Clk" = PERIOD "Clk" 10.42 ns HIGH 50 %;
 # LED
-NET "led_cathode" LOC = "P118"| IOSTANDARD = LVCMOS33 ;
+NET "led" LOC = "P118"| IOSTANDARD = LVCMOS33 ;
-NET "led_anode"   LOC = "P116"| IOSTANDARD = LVCMOS33 ;
 </source>
@@ Line 81: / Line 69: @@
 TIMESPEC "TS_Clk" = PERIOD "Clk" 10 ns HIGH 50 %;
 # LED
-NET "led_cathode" LOC = "C15"| IOSTANDARD = LVCMOS33 ; #IO_L24N_1
+NET "led" LOC = "C15"| IOSTANDARD = LVCMOS33 ; #IO_L24N_1
-NET "led_anode"   LOC = "C16"| IOSTANDARD = LVCMOS33 ; #IO_L24P_1
 </source>
@@ Line 92: / Line 79: @@
 TIMESPEC "TS_Clk" = PERIOD "Clk" 10.77 ns HIGH 50 %;
 # LED
-NET "led_cathode" LOC = "G15"| IOSTANDARD = LVCMOS33 ; #IO_L41N_GCLK8_M1CASN_1
+NET "led" LOC = "G15"| IOSTANDARD = LVCMOS33 ; #IO_L41N_GCLK8_M1CASN_1
-NET "led_anode"   LOC = "G14"| IOSTANDARD = LVCMOS33 ; #IO_L41P_GCLK9_IRDY_M1RASN_1
 </source>
@@ Line 111: / Line 97: @@
 == Generate bitstream ==
 Once these two files are written, FPGA configuration file, also named "bitstream", can be generated by clicking on ''Synthetize - XST'' then ''Implement Design'' and finally ''Generate Programming File''. If all these operations are correctly done, a file with ".bit" extension will be generated.
 == Configure FPGA ==