Difference between revisions of "DDR3-CycloneV interface description"

Latest revision as of 12:21, 21 September 2017

Introduction

2 RAMs are connected to CycloneV's APF6_SP.

Parameters

• DDR3:

General description

Diagram below describe the connections between the CycloneV and the two DDR3 blocks. Each DDR3 blocks has two banks of 128MB, on one chip (U15) all data are used, and on the other chip, only 128MB are used, the second bank is not plugged. Thus, the amount of ram accessible via the fpga is 384MB, with a data bus of 24bits.

DDR wiring diagram. Each green arrow is a 8 bits part of the data bus

To use the DDR3 SDRAM Controller with UniPhy provided by Quartus to instanciate the DDR3. See above how to do with Qsys.

DDR3 wiring for FPGA on apf6_sp

How to integrate DDR3 chips in Qsys

UniPhy Howto

This is a click howto configure the DDR3 controller in the APF6_SP.

• Once the quartus project open, select your device correctly (see the product page to now the exact part name).
• In the IP Catalog, select :

  installed IP->Library->Memory interfaces and Controllers->Memory Interfaces with UniPHY->DDR3 SDRAM Controller with UniPhy

• In the right frame select :

  JEDEC DDR3-1G6 2GB x8

• Then click on Apply
• Select checkbox Enable Hard External Memory Interface (above the 6 configs tab).
• Tab PHY Settings:
  • Speed grade : 8
  • Memory clock frequency : 375Mhz
  • PLL reference clock frequency : 62.5 Mhz
  • Rate on Avalon-MM Interface : Full
  • Supply voltage : 1.35V DDR3L
• Tab Memory parameters
  • Memory device speed grade : 400Mhz
  • Total interface width : 24
  • Row address width : 14
• Tab Controller Settings (Optionnal if you wan't to use the two DDR3 chip)
  • Select checkbox Expand Avalon-MM data for ECC
  • Select 48bits instead of 32
• Finish

Note: Using 48bits instead 32 is not standard for avalon it can be harder to connect inside your design

Clock

The hard controller IP «DDR3 SDRAM Controller with UniPHY» require using and external oscillator to clock it. On APF6_SP, the all CycloneV fpga is clocked with the PCIe clock at 62.5Mhz by default.

To force Quartus to use the coreclkout as input clock for DDR3 controller a little hack must be done after HDL code is generated.

The DDR3 clock hack

Note: If you include the .qsys under your Quartus project, Quartus will regenerate all the Qsys HDL/TCL code each times you synthesize your design, and will erase the modification.

1. Generate the design with Qsys
   1. Connect the pll_ref_clk of IP DDR3 SDRAM Controller with UniPHY on coreclkout of Avalon-MM Cyclone V Hard IP for PCI Express.
   2. Do all connections you need/want
   3. Generate the HDL code with Finish button.
2. Under Quartus include the file your_project.qip and not your_project.qsys
   1. Find the file named *_p0_pin_map.tcl :

      $ find . -name "*_p0_pin_map.tcl"

   2. It must be under directory named your_project/synthesis/submodules/
   3. Edit it and looking for line begining with :

      proc YOUR_PROJECT_NAME_mem_if_ddr3_emif_0_p0_get_input_clk_id { pll_output_node_id } {
      

   4. Add this line at the begining of function :

      return $pll_output_node_id
      

   5. Then synthesize all.

Note: In one line : $ find . -name "*_p0_pin_map.tcl" | xargs sed -iolt "/_mem_if_ddr3_emif_0_p0_get_input_clk_id {/a return \$pll_output_node_id"

Failed to find PLL reference clock

It's a known intel bug documented here.

IO

• Pinout placement
• Technology pinout

Downloads

Soon here, some examples project to downloads.

Links

• External Memory Interface Handbook
• UniPHY(pdf)
• Reference Design - Cyclone V Hard Memory Controller with Avalon MM data width expanded for User ECC
• The Clock DDR3 hack on altera website
• Debug toolkit (pdf)