OPOS6UL SP Interfaces description

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Introduction

This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named EIM for External Interface Module. All description of this bus can be found under the i.MX6UL(L) reference manual in chapter 21 (page 821).

Simplified view

Default configuration on CSx

Clocks

The clock used to clock the FPGA is EIM_BCLK (IO_L1P_CCLK_2(N12) and IO_L29P_GCLK3_2(N8)) and is configured to 99 MHz.

Chip Select

The EIM memory space is mapped into 128 MB total memory space in the processor memory. This memory space begin at address 0x50000000

Start address End address Size Name
0x5000_0000 0x57FF_FFFF 128 MB EIM (NOR/SRAM)

The total 128 MB of memory can be divided among the EIM four chip selects. See reference manual of i.MX6ULL for more information.

Timings

HDL register access examples

Pinout

FPGA Interrupt

FPGA configuration protocol

Links

<< FPGA general page