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- === Xilinx template === Xilinx provide a reset generator under its FPGA, it can be instanciated with this3 KB (336 words) - 08:35, 12 February 2015
- ** [[Vivado_installation_on_Linux|explain how to install/use Vivado Xilinx tool with APF6_SP]]34 KB (4,583 words) - 14:35, 17 March 2015
- enabled with the Cordic core (which is provided by Xilinx as a free IP).24 KB (3,993 words) - 11:24, 30 June 2010
- * FPGA: Xilinx Spartan 6 (LX9 or LX16). Default: LX92 KB (270 words) - 08:40, 12 February 2015
- if [ -z "$XILINX" ] echo "XILINX not defined"2 KB (334 words) - 14:43, 12 April 2011
- if [ -z "$XILINX" ]; then echo "XILINX not defined"1 KB (185 words) - 14:43, 12 April 2011
- [[Category: Xilinx]] ...aughter board (or with Xilinx dev-kit), thanks to PCIe, and enjoy this new Xilinx tool.2 KB (298 words) - 16:33, 30 June 2021
- [[Category: Xilinx]] Xilinx related articles402 bytes (56 words) - 16:44, 2 February 2016
- [[Category: XILINX]] * [https://www.xilinx.com/support/documentation/user_guides/ug380.pdf Spartan6 configuration] (PD8 KB (1,162 words) - 14:17, 2 June 2021