Difference between revisions of "APF51 FPGA-IMX interface description"
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* '''BCLK''': bus clock. | * '''BCLK''': bus clock. | ||
| − | * '''EB[2]''': | + | * '''EB[2]''': |
* '''CS2''': Chip select 1 corresponding to address B800_0000 | * '''CS2''': Chip select 1 corresponding to address B800_0000 | ||
* '''CS1''': Chip select 2 corresponding to address C000_0000 | * '''CS1''': Chip select 2 corresponding to address C000_0000 | ||
| Line 20: | Line 20: | ||
* '''RW''': Write signal | * '''RW''': Write signal | ||
* '''DTACK''': used as a data ack. signal for single async. accesses. | * '''DTACK''': used as a data ack. signal for single async. accesses. | ||
| − | * '''WAIT''': For burst mode, when slave is busy. | + | * '''WAIT''': For burst mode, asserted when slave is busy. |
Revision as of 17:27, 15 March 2011
Page under construction...
Informations on this page are not guaranteed !!
This article describe the interface between the i.MX51 and the Spartan6 on APF51. Documentation of i.MX interface can be found in the i.MX reference manual, chapter 63, «Wireless External Interface Module (WEIM)».
Hardware
The detailed electronic schematics of APF51 FPGA interface can be found on this document page 15.
Signals used in the design are:
- BCLK: bus clock.
- EB[2]:
- CS2: Chip select 1 corresponding to address B800_0000
- CS1: Chip select 2 corresponding to address C000_0000
- LBA: Noted ADV in reference manual.
- DA[16]: Address/Data multiplexed bus.
- CLK0: General clock for FPGA, generated by the i.MX51
- OE: Read signal
- RW: Write signal
- DTACK: used as a data ack. signal for single async. accesses.
- WAIT: For burst mode, asserted when slave is busy.
Mapping :
- CS1 -> B800_0000
- CS2 -> C000_0000
