Revision as of 14:36, 5 August 2019

<< FPGA general page

Introduction

This page describe the FPGA interfaces for APF6_SP.

Global schematic of FPGA under APF6_SP

i.MX6 to CycloneV

• IMX6-CycloneV interface description (PCIe)

DDR3 to CycloneV

• DDR3-CycloneV interface description

Pinouts

• Pinout on apf6sp hirose connector
• All pinout for PCIe, DDR3, ...

Howto

• The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O
• Use JTaG USB-Blaster to access avalon bus memory on APF6_SP FPGA

Links

• Pci debug: a tools for read/write in PCIe BAR.