Difference between revisions of "APF6 SP Interfaces description"

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This page describe the FPGA interfaces for APF6_SP.
 
This page describe the FPGA interfaces for APF6_SP.
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[[File:CycloneV_APF6_general.png|frame|center|Global schematic of FPGA under APF6_SP]]
  
 
= i.MX6 to CycloneV =
 
= i.MX6 to CycloneV =
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* [[APF6_SP_The_full_howto | The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]]
 
* [[APF6_SP_The_full_howto | The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]]
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* [[Qsys_USB_BLASTER_Jtag-avalon-MM | Use JTaG USB-Blaster to access avalon bus memory on APF6_SP FPGA]]
  
 
= Links =
 
= Links =
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* [[Pci debug]]: a tool for read/write in PCIe BAR.

Revision as of 13:36, 5 August 2019

<< FPGA general page

Introduction

This page describe the FPGA interfaces for APF6_SP.

Global schematic of FPGA under APF6_SP

i.MX6 to CycloneV

DDR3 to CycloneV

Pinouts

Howto

Links

  • Pci debug: a tool for read/write in PCIe BAR.