Difference between revisions of "APF6 SP Interfaces description"
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Revision as of 14:36, 5 August 2019
Introduction
This page describe the FPGA interfaces for APF6_SP.
Global schematic of FPGA under APF6_SP
i.MX6 to CycloneV
DDR3 to CycloneV
Pinouts
Howto
- The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O
- Use JTaG USB-Blaster to access avalon bus memory on APF6_SP FPGA
Links
- Pci debug: a tool for read/write in PCIe BAR.
