Difference between revisions of "How to make a VHDL design in Ubuntu/Debian"
(→Simulation) |
(→Simulation) |
||
| Line 30: | Line 30: | ||
Analysing files: | Analysing files: | ||
| − | |||
ghdl -i --ieee=synopsys --warn-no-vital-generic --workdir=simu --work=work src/*.vhdl testbench/testb_file.vhd | ghdl -i --ieee=synopsys --warn-no-vital-generic --workdir=simu --work=work src/*.vhdl testbench/testb_file.vhd | ||
| − | |||
And compile: | And compile: | ||
| − | |||
ghdl -m --ieee=synopsys --warn-no-vital-generic --workdir=simu --work=work testb_file | ghdl -m --ieee=synopsys --warn-no-vital-generic --workdir=simu --work=work testb_file | ||
| Line 40: | Line 37: | ||
After that a binary file named testb_file is created, to launch simulation we just have to launch | After that a binary file named testb_file is created, to launch simulation we just have to launch | ||
it | it | ||
| − | |||
./testb_file --stop-time=500ns --vcdgz=testb_file.vcdgz | ./testb_file --stop-time=500ns --vcdgz=testb_file.vcdgz | ||
| − | |||
The stop time option give the simulation time and the vcdgz option will generate a wave gunzip compressed file to visualize the result. | The stop time option give the simulation time and the vcdgz option will generate a wave gunzip compressed file to visualize the result. | ||
| Line 49: | Line 44: | ||
We can launch it with the following command : | We can launch it with the following command : | ||
| − | gunzip --stdout | + | gunzip --stdout testb_file.vcdgz | gtkwave --vcd |
== Syntesis, place & route == | == Syntesis, place & route == | ||
Revision as of 19:36, 2 March 2008
This tutorial describe how to install all tools necessary to develop simple design under ubuntu for the armadeus project. Ubuntu is a distribution based on Debian and that should work with Debian too.
Editing VHDL
To edit VHDL code all standard editing softwares like Vim, Emacs or others can be used. But Emacs has a really good vhdl-mode used by lots of designers. If you hate Emacs, you can use the xilinx-embedded editor or vim with a VHDL-plugin under development.
Making a simple project
It's a good idea to make a proper tree project for your design, because different software are used and each make a large amount of files.
Here is an exemple of VHDL project tree :
- MySimple_project/
- src/ for all sources files (.vhd,.ucf,.xcf)
- testbench/ VHDL sources files for testing your design
- ise/ Xilinx web pack will work in this directory
- simu/ All files generated by the simulator
Simulation
To stay in the free spirit, the best method to simulate is to use ghdl. GHDL is based on gcc, to install it on Ubuntu you just have to type :
sudo apt-get install ghdl
You can find a good tutorial for using ghdl here and on the official website. It's supposed that the project tree used is this one see above.
Analysing files:
ghdl -i --ieee=synopsys --warn-no-vital-generic --workdir=simu --work=work src/*.vhdl testbench/testb_file.vhd
And compile:
ghdl -m --ieee=synopsys --warn-no-vital-generic --workdir=simu --work=work testb_file
After that a binary file named testb_file is created, to launch simulation we just have to launch
it
./testb_file --stop-time=500ns --vcdgz=testb_file.vcdgz
The stop time option give the simulation time and the vcdgz option will generate a wave gunzip compressed file to visualize the result.
Visualizing result can be done with gtkwave:
sudo apt-get install gtkwave
We can launch it with the following command :
gunzip --stdout testb_file.vcdgz | gtkwave --vcd
