Difference between revisions of "How to simulate post synthesis and post place & route design with GHDL"
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− | To simulate post synthesis and post place&route design made with ISE webpack, two library must be used : | + | [[Category: FPGA]] |
+ | To simulate post synthesis and post place&route design made with ISE webpack, | ||
+ | two library must be used : | ||
− | * UNISIM : for post synthesis simulation. | + | * UNISIM : for Xilinx primitive instance and post synthesis simulation. |
* SIMPRIM : for post place&route simulation. | * SIMPRIM : for post place&route simulation. | ||
− | VHDL sources of this two libraries are provided by Xilinx under ''$XILINX/vhdl/src/'' directory (see xilinx [http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/simu5.html explanation]) . | + | VHDL sources of this two libraries are provided by Xilinx under |
+ | ''$XILINX/vhdl/src/'' directory (see xilinx | ||
+ | [http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/simu5.html explanation]) . | ||
= Generate post synthesis/place&route file = | = Generate post synthesis/place&route file = | ||
− | To generate '''Post-synthesis''' file, just double-click on "''Synthesize - XST -> Generate Post-Synthesize simulation Model''" | + | To generate '''Post-synthesis''' file, just double-click on "''Synthesize - XST |
+ | -> Generate Post-Synthesize simulation Model''" | ||
− | To generate '''Post-Place & route''' file, just double-click on "''implement design -> Place & Route -> generate Post-place & route simulation Model''" and don't forget to select VHDL as preferred language in project properties. | + | To generate '''Post-Place & route''' file, just double-click on "''implement |
− | The file will be generated in ''$PROJECT_DIR/netgen/par/top_biled_timesim.vhd''. | + | design -> Place & Route -> generate Post-place & route simulation Model''" and |
+ | don't forget to select VHDL as preferred language in project properties. The | ||
+ | file will be generated in ''$PROJECT_DIR/netgen/par/top_biled_timesim.vhd''. | ||
− | = Compile UNISIM and SIMPRIM with GHDL = | + | = Compile UNISIM and SIMPRIM with GHDL (on linux) = |
− | + | Sources of libraries can be found in ''$XILINX/vhdl/src/unisims'' and | |
+ | ''$XILINX/vhdl/src/simprims''. To compile it, Walter F.J. Mueller made three | ||
+ | perl scripts (for more information see his | ||
+ | [https://mail.gna.org/public/ghdl-discuss/2007-10/msg00016.html mail]): | ||
− | + | * [[xilinx_vhdl_chop]] | |
− | + | ||
+ | For ISE 10.x | ||
+ | * [[xilinx_ghdl_unisim]] | ||
+ | * [[xilinx_ghdl_simprim]] | ||
+ | For ISE 12.x and 13.x | ||
+ | * [[xilinx_ghdl_unisim_12.x]] | ||
+ | * [[xilinx_ghdl_simprim_12.x]] | ||
+ | |||
+ | Copy ''xilinx_vhdl_chop'' under ''/usr/local/bin'' directory, and be sure that ''/usr/local/bin'' is under your $PATH. | ||
+ | Copy ''xilinx_ghdl_unisim'' and ''xilinx_ghdl_simprim'' under a directory and make it executable (chmod 755 script_name). | ||
+ | |||
+ | Define $XILINX path before launch ''xilinx_ghdl_unisim'' and ''xilinx_ghdl_simprim'' to compile libraries. | ||
+ | <source lang="bash"> | ||
+ | $export XILINX=/opt/Xilinx/10.1/ISE/ | ||
+ | $./xilinx_ghdl_unisim | ||
+ | ... | ||
+ | $./xilinx_ghdl_simprim | ||
+ | ... | ||
+ | </source> | ||
+ | |||
+ | Some files will have compilations error, it's known but not normal ! | ||
+ | |||
+ | Compiled libraries will be found in ''$XILINX/ghdl/unisims/'' and ''$XILINX/ghdl/simprims/''. | ||
= Simulate with GHDL = | = Simulate with GHDL = | ||
+ | |||
+ | Now, we need two files: | ||
+ | * the testbench wrote in vhdl : testbench.vhd | ||
+ | * the post-synthesis file wrote in vhdl too : post_synthesis.vhd | ||
+ | |||
+ | First, we have to analyse the design : | ||
+ | ghdl -i --ieee=synopsys -P$XILINX/ghdl/unisim --warn-no-vital-generic --work=work testbench.vhd post_synthesis.vhd | ||
+ | |||
+ | Then simulate: | ||
+ | ghdl -m --ieee=synopsys -P$XILINX/ghdl/unisim --warn-no-vital-generic --work=work top_module_name | ||
+ | |||
+ | To simulate post-place and route, do the same but with ''-P$XILINX/ghdl/simprim'' option. | ||
+ | |||
+ | =Links= | ||
+ | * http://forum.ubuntu-fr.org/viewtopic.php?pid=1545563 |
Latest revision as of 09:37, 12 February 2015
To simulate post synthesis and post place&route design made with ISE webpack, two library must be used :
- UNISIM : for Xilinx primitive instance and post synthesis simulation.
- SIMPRIM : for post place&route simulation.
VHDL sources of this two libraries are provided by Xilinx under $XILINX/vhdl/src/ directory (see xilinx explanation) .
Contents
Generate post synthesis/place&route file
To generate Post-synthesis file, just double-click on "Synthesize - XST -> Generate Post-Synthesize simulation Model"
To generate Post-Place & route file, just double-click on "implement design -> Place & Route -> generate Post-place & route simulation Model" and don't forget to select VHDL as preferred language in project properties. The file will be generated in $PROJECT_DIR/netgen/par/top_biled_timesim.vhd.
Compile UNISIM and SIMPRIM with GHDL (on linux)
Sources of libraries can be found in $XILINX/vhdl/src/unisims and $XILINX/vhdl/src/simprims. To compile it, Walter F.J. Mueller made three perl scripts (for more information see his mail):
For ISE 10.x
For ISE 12.x and 13.x
Copy xilinx_vhdl_chop under /usr/local/bin directory, and be sure that /usr/local/bin is under your $PATH. Copy xilinx_ghdl_unisim and xilinx_ghdl_simprim under a directory and make it executable (chmod 755 script_name).
Define $XILINX path before launch xilinx_ghdl_unisim and xilinx_ghdl_simprim to compile libraries.
$export XILINX=/opt/Xilinx/10.1/ISE/
$./xilinx_ghdl_unisim
...
$./xilinx_ghdl_simprim
...
Some files will have compilations error, it's known but not normal !
Compiled libraries will be found in $XILINX/ghdl/unisims/ and $XILINX/ghdl/simprims/.
Simulate with GHDL
Now, we need two files:
- the testbench wrote in vhdl : testbench.vhd
- the post-synthesis file wrote in vhdl too : post_synthesis.vhd
First, we have to analyse the design :
ghdl -i --ieee=synopsys -P$XILINX/ghdl/unisim --warn-no-vital-generic --work=work testbench.vhd post_synthesis.vhd
Then simulate:
ghdl -m --ieee=synopsys -P$XILINX/ghdl/unisim --warn-no-vital-generic --work=work top_module_name
To simulate post-place and route, do the same but with -P$XILINX/ghdl/simprim option.