Difference between revisions of "How to simulate post synthesis and post place & route design with GHDL"
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| − | To simulate post synthesis and post place&route design made with ISE webpack, two library must be used : | + | To simulate post synthesis and post place&route design made with ISE webpack, |
| + | two library must be used : | ||
* UNISIM : for post synthesis simulation. | * UNISIM : for post synthesis simulation. | ||
* SIMPRIM : for post place&route simulation. | * SIMPRIM : for post place&route simulation. | ||
| − | VHDL sources of this two libraries are provided by Xilinx under ''$XILINX/vhdl/src/'' directory (see xilinx [http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/simu5.html explanation]) . | + | VHDL sources of this two libraries are provided by Xilinx under |
| + | ''$XILINX/vhdl/src/'' directory (see xilinx | ||
| + | [http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/simu5.html | ||
| + | explanation]) . | ||
= Generate post synthesis/place&route file = | = Generate post synthesis/place&route file = | ||
| − | To generate '''Post-synthesis''' file, just double-click on "''Synthesize - XST -> Generate Post-Synthesize simulation Model''" | + | To generate '''Post-synthesis''' file, just double-click on "''Synthesize - XST |
| + | -> Generate Post-Synthesize simulation Model''" | ||
| − | To generate '''Post-Place & route''' file, just double-click on "''implement design -> Place & Route -> generate Post-place & route simulation Model''" and don't forget to select VHDL as preferred language in project properties. | + | To generate '''Post-Place & route''' file, just double-click on "''implement |
| − | The file will be generated in ''$PROJECT_DIR/netgen/par/top_biled_timesim.vhd''. | + | design -> Place & Route -> generate Post-place & route simulation Model''" and |
| + | don't forget to select VHDL as preferred language in project properties. The | ||
| + | file will be generated in ''$PROJECT_DIR/netgen/par/top_biled_timesim.vhd''. | ||
| − | = Compile UNISIM and SIMPRIM with GHDL = | + | = Compile UNISIM and SIMPRIM with GHDL (on linux) = |
| − | + | Sources of libraries can be found in ''$XILINX/vhdl/src/unisims'' and | |
| + | ''$XILINX/vhdl/src/simprims''. To compile it, Walter F.J. Mueller made tree | ||
| + | perl scripts (for more information see his | ||
| + | [https://mail.gna.org/public/ghdl-discuss/2007-10/msg00016.html mail]): | ||
| − | + | * [[xilinx_vhdl_chop]] | |
| − | + | * [[xilinx_ghdl_unisim]] | |
| + | * [[xilinx_ghdl_simprim]] | ||
| + | |||
| + | Copy its under a directory and make it executable (chmod 755 script_name). | ||
| + | |||
| + | Launch ''xilinx_ghdl_unisim'' and ''xilinx_ghdl_simprim'' to compile libraries. | ||
| + | Some files will have compilations error, it's known but not normal ! | ||
| + | |||
| + | Compiled libraries will be found in ''$XILINX/ghdl/unisims/'' and ''$XILINX/ghdl/simprims/''. | ||
= Simulate with GHDL = | = Simulate with GHDL = | ||
| + | |||
| + | Now, we need two files: | ||
| + | * the testbench wrote in vhdl : testbench.vhd | ||
| + | * the post-synthesis file wrote in vhdl too : post_synthesis.vhd | ||
| + | |||
| + | First, we have to analyse the design : | ||
| + | ghdl -i --ieee=synopsys -P$XILINX/ghdl/simprim --warn-no-vital-generic --work=work testbench.vhd post_synthesis.vhd | ||
| + | |||
| + | Then simulate: | ||
| + | ghdl -m --ieee=synopsys -P$XILINX/ghdl/simprim --warn-no-vital-generic --work=work top_module_name | ||
Revision as of 10:19, 10 October 2008
To simulate post synthesis and post place&route design made with ISE webpack, two library must be used :
- UNISIM : for post synthesis simulation.
- SIMPRIM : for post place&route simulation.
VHDL sources of this two libraries are provided by Xilinx under $XILINX/vhdl/src/ directory (see xilinx [http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/simu5.html explanation]) .
Generate post synthesis/place&route file
To generate Post-synthesis file, just double-click on "Synthesize - XST -> Generate Post-Synthesize simulation Model"
To generate Post-Place & route file, just double-click on "implement design -> Place & Route -> generate Post-place & route simulation Model" and don't forget to select VHDL as preferred language in project properties. The file will be generated in $PROJECT_DIR/netgen/par/top_biled_timesim.vhd.
Compile UNISIM and SIMPRIM with GHDL (on linux)
Sources of libraries can be found in $XILINX/vhdl/src/unisims and $XILINX/vhdl/src/simprims. To compile it, Walter F.J. Mueller made tree perl scripts (for more information see his mail):
Copy its under a directory and make it executable (chmod 755 script_name).
Launch xilinx_ghdl_unisim and xilinx_ghdl_simprim to compile libraries. Some files will have compilations error, it's known but not normal !
Compiled libraries will be found in $XILINX/ghdl/unisims/ and $XILINX/ghdl/simprims/.
Simulate with GHDL
Now, we need two files:
- the testbench wrote in vhdl : testbench.vhd
- the post-synthesis file wrote in vhdl too : post_synthesis.vhd
First, we have to analyse the design : ghdl -i --ieee=synopsys -P$XILINX/ghdl/simprim --warn-no-vital-generic --work=work testbench.vhd post_synthesis.vhd
Then simulate: ghdl -m --ieee=synopsys -P$XILINX/ghdl/simprim --warn-no-vital-generic --work=work top_module_name
