How to simulate post synthesis and post place & route design with GHDL
From ArmadeusWiki
Revision as of 17:07, 9 October 2008 by FabienM (Talk | contribs) (New page: To simulate post synthesis and post place&route design made with ISE webpack, two library must be used : * UNISIM : for post synthesis simulation. * SIMPRIM : for post place&route simulat...)
To simulate post synthesis and post place&route design made with ISE webpack, two library must be used :
- UNISIM : for post synthesis simulation.
- SIMPRIM : for post place&route simulation.
VHDL sources of this two libraries are provided by Xilinx under $XILINX/vhdl/src/ directory (see xilinx explanation) .
Generate post synthesis/place&route file
To generate Post-synthesis file, just double-click on "Synthesize - XST -> Generate Post-Synthesize simulation Model"
To generate Post-Place & route file, just double-click on "implement design -> Place & Route -> generate Post-place & route simulation Model" and don't forget to select VHDL as preferred language in project properties. The file will be generated in $PROJECT_DIR/netgen/par/top_biled_timesim.vhd.
