Difference between revisions of "IMX27-Spartan3A interface description"

Revision as of 11:54, 23 January 2012

Introduction

This article describes the bus interface configuration to communicate between the i.MX27 processor and the Spartan3A FPGA of the APF27 board.

Simplified view

figure 1 - i.MX27-Spartan3A bus description

Figure 1 is a simplified view of apf27 schematics (page 11). Signals are :

• DATA[15:0]: Data bus.
• ADDR[12:1]: Address bus. All access are done in 16bits, this means that A0 is not used and not connected.
• CS4N_DTACK: Chip select 4 (0xD400_0000 to 0xD5FF_FFFF ) or Data Transmit ACKnowledge. This signal can be used as DTACK for asynchronous access with chip select 5.
• CS5N: Chip select 5 (0xD600_0000 to 0xD7FF_FFFF ). Chip select 5. Configured by default for FPGA communication.
• CS1N: Chip select 1 (0xC800_0000 to 0xCFFF_FFFF ). Chip select 1
• EB0N, EB1N: For Enable Byte, write signal for lower byte and upper byte on data bus.
• OEN: For Output Enable bit, read signal.
• DMA_GRANT#: Required for DMA access (future development).
• DMA_REQ#: Required for DMA access (future development)

Not part of WEIM bus :

• CLKO: Clock generated by the i.MX. Used as a general clock by the FPGA.
• FPGA_INIT: Not part of i.MX27 WEIM bus but used by default for interrupts (GPIO PF12).

Signals in bold are used in default configuration. Some others signals are used only for firmware download. For more informations about the FPGA wiring, see the APF27 schematics and the i.MX27 reference manual, especially the WEIM chapter.

Default configuration on CS5N

Clock

The clock used to clock the fpga is CLK0 and is configured to 100 MHz.

Chip select

By default the chip select 5 (CS5N) is used for communication. The address domain corresponding to this chip select can be found in i.MX27 reference manual in chapter 2 (Secondary AHB Port 2 Memory Map page 129).

Other chip select (CS1 and CS4) can be used to extend the memory domain or to use different timing configuration with the same Address/Data bus signals. The default bus configuration for the APF27 can be found in the file apf27.h in u-boot sources : buildroot/target/device/armadeus/apf27/apf27-u-boot-1.3.4.h

Especially these lines :

/* FPGA 16 bit data bus */
#define CFG_CS5U_VAL	0x00000600
#define CFG_CS5L_VAL	0x00000D01
#define CFG_CS5A_VAL	0

Note: Do not forget to do : $ make u-boot-dirclean $ make To test your modification under the apf27-u-boot-1.3.4.h file

It is not necessary to modify apf27.h file and recompile U-Boot for WEIM timings test, register can be read/written via U-Boot or Linux. To access these register with U-Boot or Linux, use the address given under the reference manual in WEIM register descriptions (17.5.3 Register Descriptions).

Timings

Following chronograms represent WEIM read and write configured for APF27.

figure 2 - WEIM Write timings

figure 3 - WEIM Read timings

FPGA side

By default, the wishbone bus is proposed on the spartan3A fpga. A WEIM to Wishbone wrapper is used, which is available under POD default libraries in wrappers lib. The component is named imx27_wb16_wrapper.

The FPGA interrupt

By default under POD the pin FPGA_INIT (PF12) is used for the interrupt manager irq_mngr. For simple user application the gpio can be used with the GPIOlib interface, the gpio number will then be (6-1)x32+12 = 172.

Note : With default apf27 kernel 2.6.29.x the GPIOlib can use interrupt event, but can't configure it with /sys/class/gpio/gpio172/edge file. Interrupt must be configured under the kernel sources. The /sys/class/gpio/gpio172/edge file can be use only with kernel 2.6.38.x.

Pinout