Difference between revisions of "Migen"
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== Links == | == Links == | ||
| − | + | * [https://github.com/m-labs/migen Migen Code repository] | |
* [http://m-labs.hk/gateware.html Official migen presentation] | * [http://m-labs.hk/gateware.html Official migen presentation] | ||
* [http://connect.ed-diamond.com/GNU-Linux-Magazine/GLMF-149/Migen-une-boite-a-outils-en-Python-pour-concevoir-des-circuits-logiques-complexes An article on the french Linux Magasine 149] | * [http://connect.ed-diamond.com/GNU-Linux-Magazine/GLMF-149/Migen-une-boite-a-outils-en-Python-pour-concevoir-des-circuits-logiques-complexes An article on the french Linux Magasine 149] | ||
* [http://www.martoni.fr/wordpress/?p=706 Some experiments for apf27 (fr)] | * [http://www.martoni.fr/wordpress/?p=706 Some experiments for apf27 (fr)] | ||
Revision as of 10:58, 17 July 2014
Introduction
Migen is a python module that make FPGA design possible without VHDL or Verilog. Writing a Migen design for fpga is like writing python programme. If it's correctly configured with ISE or Quartus, Migen is capable of generating the bitstream directly.
APF27 and APF51 platform has been integred under Migen module, then design can be done with it for these APF.
Blink led Example
APF27
#!/usr/local/bin/python3.4
# -*- coding: utf-8 -*-
from migen.fhdl.std import *
from mibuild.generic_platform import Pins, IOStandard
from mibuild.platforms import apf27
ios = [
("user_led", 0, Pins("J2:22"), IOStandard("LVCMOS33"))
]
plat = apf27.Platform()
plat.add_extension(ios)
led = plat.request("user_led", 0) # led pin on apf27dev
m = Module()
counter = Signal(26)
m.comb += led.eq(counter[25])
m.sync += counter.eq(counter + 1)
plat.build_cmdline(m)
APF51
#!/usr/local/bin/python3.4
# -*- coding: utf-8 -*-
from migen.fhdl.std import *
from mibuild.generic_platform import Pins, IOStandard
from mibuild.platforms import apf51
ios = [
("user_led", 0, Pins("J2:15"), IOStandard("LVCMOS33"))
]
plat = apf51.Platform()
plat.add_extension(ios)
led = plat.request("user_led", 0) # led pin on apf51dev
m = Module()
counter = Signal(26)
m.comb += led.eq(counter[25])
m.sync += counter.eq(counter + 1)
plat.build_cmdline(m)
