Difference between revisions of "OPOS6UL SP Interfaces description"

From ArmadeusWiki
Jump to: navigation, search
(Default configuration on CSx)
m (HDL register access example)
Line 22: Line 22:
 
=== Timings ===
 
=== Timings ===
  
=== HDL register access example ===
+
=== HDL register access examples ===
  
 
=== Pinout ===
 
=== Pinout ===

Revision as of 07:52, 12 September 2018


Page under construction... Construction.png Informations on this page are not guaranteed !!

Introduction

This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named EIM for External Interface Module.


Simplified view

Default configuration on CSx

Clocks

Chip Select

Timings

HDL register access examples

Pinout

FPGA Interrupt

FPGA configuration protocol

Links

<< FPGA general page