Difference between revisions of "OPOS6UL SP Interfaces description"

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(Default configuration on CSx)
(FPGA configuration protocol)
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=== Timings ===
 
=== Timings ===
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== FPGA Interrupt ==
  
 
== FPGA configuration protocol ==
 
== FPGA configuration protocol ==

Revision as of 07:50, 12 September 2018


Page under construction... Construction.png Informations on this page are not guaranteed !!

Introduction

This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named EIM for External Interface Module.


Simplified view

Default configuration on CSx

Clocks

Chip Select

Timings

FPGA Interrupt

FPGA configuration protocol

Links

<< FPGA general page