Difference between revisions of "PCIe FPGA loading"

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Revision as of 12:23, 17 March 2015


On APF6_SP it's possible to use the PCI express bus to configure the FPGA (cycloneV). This article describe how to do that.

Generate files

Quartus configuration

Your design must include the PCIe and CvP components. Once the project synthesized, open the menu:

File -> Convert Programming Files ...
  • In Output programming file select the programming file type: Raw Binary File (.rbf).
  • In Input files to convert clic on Add Files... and add your binary.sof file.
  • In Output programming file check the option Create CvP files (Generate binary.periph.rbf and binary.core.rbf)
  • Click on Generate

You will get two files:

  • binary.periph.rbf: peripheral config file to be loaded via serial config bus with U-Boot
  • binary.core.rbf: core config file to be loaded via PCIe bus with Linux.

Linux configuration

All drivers are already selected by default in APF6's Buildroot configuration.

Configure the FPGA

Peripheral configuration in uboot

PCIe must be activated before Linux boot. To do that, just load the peripheral bitstream with uboot :

BIOS> tftpboot ${loadaddr}
BIOS> fpga load 0 ${loadaddr} ${filesize}

Then boot Linux:

BIOS> boot

Core configuration in Linux

The PCIe device must be seen in lspci command in Linux :

# lspci
00:00.0 PCI bridge: Device 16c3:abcd (rev 01)
01:00.0 Unclassified device [0013]: Altera Corporation Device e001 (rev 01)

You can then download the core ( should be replaced with your Host PC IP address):

$ tftp -g -r binary.core.rbf
$ modprobe fpgaloader
$ mknod /dev/altera_cvp c 249 0
$ cat output_file.core.rbf > /dev/altera_cvp
Altera CvP 0000:01:00.0: Now starting CvP...
Altera CvP 0000:01:00.0: CvP successful, application layer now ready