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  • [[Category: Spartan6]] ...he bus interface configuration to communicate between i.MX51 processor and Spartan6 FPGA. In i.MX51, the bus used to make communication with the FPGA is named
    5 KB (663 words) - 16:57, 19 March 2019

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  • * [[APF51]]: i.MX51 based module with Spartan6 FPGA * [[OPOS6UL_SP]] : i.MX6ULL based module with a Spartan6 FPGA
    2 KB (341 words) - 14:14, 22 August 2018
  • * '''APF51''': [[IMX51-Spartan6 interface description]]
    4 KB (515 words) - 15:23, 29 April 2019
  • This article describe the interface between the i.MX51 and the Spartan6 on [[APF51]].
    1 KB (160 words) - 18:37, 15 March 2011
  • The SP_Vision board is an extension of [[APF27Dev]] and [[APF51Dev]] with a Spartan6 and two DDR. It is designed for real-time video processing.
    2 KB (299 words) - 18:18, 4 September 2013
  • u-boot-2010.03-321-add_spartan6.patch: add spartan6 driver u-boot-2010.03-322-fpga_second_load_operator.patch: support spartan6 - spartan6 for apf27
    15 KB (2,370 words) - 10:39, 8 September 2013
  • [[Category: Spartan6]] ...he bus interface configuration to communicate between i.MX51 processor and Spartan6 FPGA. In i.MX51, the bus used to make communication with the FPGA is named
    5 KB (663 words) - 16:57, 19 March 2019
  • [[Category: Spartan6]] ...le describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named ''
    6 KB (922 words) - 14:51, 29 April 2019
  • * FPGA: [https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html Spartan6 LX9] * [[OPOS6UL_SP_Interfaces_description | Spartan6]]
    2 KB (192 words) - 16:54, 29 April 2019