Difference between revisions of "Using FPGA"
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* '''APF51''': [[IMX51-Spartan6 interface description]] | * '''APF51''': [[IMX51-Spartan6 interface description]] | ||
* '''APF6_SP''': [[APF6_SP Interfaces description]] | * '''APF6_SP''': [[APF6_SP Interfaces description]] | ||
+ | * '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]] | ||
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* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]] | * [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]] | ||
+ | '''Lattice''' | ||
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+ | * [[IceCube | Install IceCube]] | ||
+ | * [[Diamond | Install Lattice Diamond]] | ||
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+ | '''Microsemi''' | ||
+ | * [[Libero | Install Libero]] | ||
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For complex projects, POD should be used to simplify design. | For complex projects, POD should be used to simplify design. | ||
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+ | === HDL === | ||
===VHDL === | ===VHDL === | ||
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=== Verilog === | === Verilog === | ||
+ | * [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator | ||
+ | * [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator | ||
+ | * [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification | ||
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+ | === Synthesizable Synchronous HDL === | ||
+ | ==== [[Migen]] ==== | ||
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+ | With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis. | ||
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+ | ==== [[Chisel]] ==== | ||
+ | With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis. Armadeus system can help you to integrate a Chisel project on Armadeus board. | ||
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''' CycloneV''' | ''' CycloneV''' | ||
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera] | * [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera] | ||
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+ | ''' OpenSource ''' | ||
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+ | * [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map] | ||
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Revision as of 14:41, 30 October 2018
Developing on the APF FPGA
FPGA Interfaces
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Using Armadeus FPGAManage the FPGA from Armadeus distribution.
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Make some examplesThese examples give the basis to make VHDL design for FPGA.
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Design ToolsDescription of tools used to simulate, to synthesize, and to download/configure FGPA. Xilinx Altera Lattice Microsemi |
Automatize FPGA design makingPeripherals On DemandFor complex projects, POD should be used to simplify design.
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HDLVHDL
Verilog
Synthesizable Synchronous HDLMigenWith migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis. ChiselWith Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis. Armadeus system can help you to integrate a Chisel project on Armadeus board. |
LinksSome useful links. Wishbone Spartan CycloneV OpenSource |
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