Difference between revisions of "Using FPGA"

From ArmadeusWiki
Jump to: navigation, search
(FPGA Interfaces)
(FPGA Interfaces)
Line 12: Line 12:
 
=== FPGA Interfaces ===
 
=== FPGA Interfaces ===
  
* [[APF9328]] : [[IMX9328-Spartan3 interface description]]
+
====[[APF9328]]====
* [[APF27]] : [[IMX27-Spartan3A interface description]]
+
* [[IMX9328-Spartan3 interface description]]
* [[APF51]] : [[IMX51-Spartan6 interface description]]
+
====[[APF27]]====
* [[APF6_SP]]:
+
* [[IMX27-Spartan3A interface description]]
** [[IMX6-CycloneV interface description | IMX6-CycloneV interface description (PCIe)]]
+
==== [[APF51]] ====
** [[DDR3-CycloneV interface description | DDR3-CycloneV interface description]]
+
* [[IMX51-Spartan6 interface description]]
** [[APF6_SP hirose pinout | Pinout on apf6sp hirose connector]]
+
==== [[APF6_SP]] ====
 +
* [[IMX6-CycloneV interface description | IMX6-CycloneV interface description (PCIe)]]
 +
* [[DDR3-CycloneV interface description | DDR3-CycloneV interface description]]
 +
* [[APF6_SP hirose pinout | Pinout on apf6sp hirose connector]]
  
  

Revision as of 14:15, 1 February 2016


Developing on the APF FPGA

FPGA Interfaces

APF9328

APF27

APF51

APF6_SP


Using Armadeus FPGA

Manage the FPGA from Armadeus distribution.



Make some examples

These examples give the basis to make VHDL design for FPGA.



Design Tools

Description of tools used to simulate, to synthesize, and to download/configure FGPA.

Xilinx

Altera


Automatize FPGA design making

Peripherals On Demand

For complex projects, POD should be used to simplify design.

Migen

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

Chisel

With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis.

VHDL

Verilog

Links

Some useful links.

Wishbone

Spartan

CycloneV