Difference between revisions of "Using FPGA"

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(Design Tools)
(FPGA Interfaces)
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=== FPGA Interfaces ===
 
=== FPGA Interfaces ===
  
====[[APF9328]]====
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'''APF9328''': [[IMX9328-Spartan3 interface description]]
* [[IMX9328-Spartan3 interface description]]
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'''APF27''': [[IMX27-Spartan3A interface description]]
====[[APF27]]====
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'''APF51''': [[IMX51-Spartan6 interface description]]
* [[IMX27-Spartan3A interface description]]
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'''APF6_SP''': [[APF6_SP Interfaces description]]
==== [[APF51]] ====
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* [[IMX51-Spartan6 interface description]]
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==== [[APF6_SP]] ====
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* [[APF6_SP_The_full_howto | The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]]
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* [[IMX6-CycloneV interface description | IMX6-CycloneV interface description (PCIe)]]
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* [[DDR3-CycloneV interface description | DDR3-CycloneV interface description]]
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* [[APF6_SP hirose pinout | Pinout on apf6sp hirose connector]]
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Revision as of 10:10, 3 February 2016


Developing on the APF FPGA

FPGA Interfaces

APF9328: IMX9328-Spartan3 interface description APF27: IMX27-Spartan3A interface description APF51: IMX51-Spartan6 interface description APF6_SP: APF6_SP Interfaces description

Using Armadeus FPGA

Manage the FPGA from Armadeus distribution.

Make some examples

These examples give the basis to make VHDL design for FPGA.



Design Tools

Description of tools used to simulate, to synthesize, and to download/configure FGPA.

Xilinx

Altera


Automatize FPGA design making

Peripherals On Demand

For complex projects, POD should be used to simplify design.

Migen

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

Chisel

With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis.

VHDL

Verilog

Links

Some useful links.

Wishbone

Spartan

CycloneV