Using FPGA

From ArmadeusWiki
Jump to: navigation, search


Developing on the APF FPGA

FPGA Interfaces

Using Armadeus FPGA

Manage the FPGA from Armadeus distribution.

Make some examples

These examples give the basis to make VHDL design for FPGA.



Design Tools

Description of tools used to simulate, to synthesize, and to download/configure FGPA.

Xilinx

Altera

Lattice

Microsemi

Automatize FPGA design making

Peripherals On Demand

For complex projects, POD should be used to simplify design.

FuseSoC

FuseSoC is a builder written in Python used to automatize FPGA constructions

HDL

VHDL

Verilog

  • Verilator an High speed verilog simulator
  • Icarus Famous open-source verilog simulator
  • SymbiYosys open-source Verilog formal verification

Synthesizable Synchronous HDL

Migen

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

Chisel

With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

Links

Some useful links.

Wishbone

Spartan

CycloneV

OpenSource