Difference between revisions of "OPOS6UL SP Interfaces description"

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== Introduction ==
 
== Introduction ==
  
This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named '''EIM''' for '''E'''xternal '''I'''nterface '''M'''odule.
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This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named '''EIM''' for '''E'''xternal '''I'''nterface '''M'''odule. All description of this bus can be found under the i.MX6UL(L) reference manual in chapter 21 (page 821).
 
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== Simplified view ==
 
== Simplified view ==

Revision as of 07:53, 12 September 2018


Page under construction... Construction.png Informations on this page are not guaranteed !!

Introduction

This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named EIM for External Interface Module. All description of this bus can be found under the i.MX6UL(L) reference manual in chapter 21 (page 821).

Simplified view

Default configuration on CSx

Clocks

Chip Select

Timings

HDL register access examples

Pinout

FPGA Interrupt

FPGA configuration protocol

Links

<< FPGA general page