Difference between revisions of "OPOS6UL SP Interfaces description"
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== Links == | == Links == | ||
| − | * [https://www.nxp.com/docs/en/reference-manual/IMX6ULLRM.pdf i.MX6UL(L) reference manual](PDF chapter 21 page 821) | + | * [https://www.nxp.com/docs/en/reference-manual/IMX6ULLRM.pdf i.MX6UL(L) reference manual] (PDF chapter 21 page 821) |
| + | * [https://www.nxp.com/docs/en/data-sheet/IMX6ULLIEC.pdf i.MX6UL(L) Datasheet] (PDF) | ||
[[Using_FPGA| << FPGA general page]] | [[Using_FPGA| << FPGA general page]] | ||
Revision as of 09:02, 12 September 2018
Page under construction...
Informations on this page are not guaranteed !!
Contents
Introduction
This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named EIM for External Interface Module. All description of this bus can be found under the i.MX6UL(L) reference manual in chapter 21 (page 821).
Simplified view
Default configuration on CSx
Clocks
Chip Select
Timings
HDL register access examples
Pinout
FPGA Interrupt
FPGA configuration protocol
Links
- i.MX6UL(L) reference manual (PDF chapter 21 page 821)
- i.MX6UL(L) Datasheet (PDF)
