Difference between revisions of "A simple design with Wishbone bus"

Revision as of 12:06, 17 March 2008

PAGE UNDER CONSTRUCTION !!!

This article intended to explain how to design Wishbone compatible components with simple example. The design can be found in sourceforge tree.

Description of wishbone structure for armadeus can be found here in french.

General structure

The main functionality of this component is to do the same things that benoît project : switch on a led when a button is pressed.

But to learn about designing Wishbone component and linux driver, the design is little bit more complicated (!).

When button is pressed, the component Wb_button send interrupt signal to irq_mngr. irq_mngr will toggle a flag and send interruption to i.mx processor. A Linux driver on i.mx will read irq_mngr and acknowledge irq by writing '1' on a register. And finally, Linux driver will toggle led value by writing on led register.

imx_wrapper, syscon and irq_mngr are standards ARMadeus-Wishbone IPs that just been instantiated in our design.

Wb_button and Wb_led are simple slave component we want to integrate in the FPGA.

All these components are connected together with the 'glue logic' component intercon.

Wishbone slave application components

Wb_led

This component is a simple 16-bit Wishbone slave output port, from wishbone specification example (p110).

It is a simple register, that can be read and write. The led is controled with register pin 0.

-----------------------------------------------------------------------
Architecture Wb_led_1 of Wb_led is                   
-----------------------------------------------------------------------
  signal reg : std_logic_vector( 15 downto 0);
begin                                                
    
-- connect led                                       
LED <= reg(0);    
    
-- manage register
reg_bloc : process(gls_clk,gls_reset)                
begin
  if gls_reset = '1' then                            
    reg <= (others => '0');
  elsif rising_edge(gls_clk) then                    
    if ((wbs_strobe and wbs_write) = '1' ) then      
      reg <= wbs_writedata;                          
    else                                             
      reg <= reg;
    end if;
  end if;
  
end process reg_bloc;
  
wbs_ack <= wbs_strobe;
wbs_readdata <= reg;                                 
                                                     
end architecture Wb_led_1;

Wb_button

Wishbone specific components

irq_mngr

syscon

imx_wrapper

intercon : the glue logic