Difference between revisions of "CAN bus Linux sja1000"

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(New page: {{Under_Construction}} This page explain how to communicate with a CAN bus through the CAN controller SJA1000 and a TJA1040 CAN Transceiver. ==Hardware Requirements== * APF27-Dev and APF...)
 
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 +
This page explain how to communicate with a CAN bus through the SJA1000 CAN controller and a TJA1040 CAN Transceiver.
 +
{{Warning| There is no SJA1000 CAN controller on ARMadeus boards, you have to create your own assembly. The assembly used for doing this test is given on this page.}}
 +
 +
 
{{Under_Construction}}
 
{{Under_Construction}}
  
−
This page explain how to communicate with a CAN bus through the CAN controller SJA1000 and a TJA1040 CAN Transceiver.
+
== Hardware Requirements ==
  
−
==Hardware Requirements==
 
 
* APF27-Dev and APF27 with FPGA Spartan 3A
 
* APF27-Dev and APF27 with FPGA Spartan 3A
 
* 8 bits transceiver 74LVXC3245 (2x)
 
* 8 bits transceiver 74LVXC3245 (2x)
Line 11: Line 14:
 
* Resistors and capacitances
 
* Resistors and capacitances
  
−
==Realisation==
+
== Realisation ==
−
Foremost, you have to create the following mounting
+
Foremost, you have to create the following assembly
  
 
[[Image:Sja1000-APF27Dev-Mounting.png | 800px]]
 
[[Image:Sja1000-APF27Dev-Mounting.png | 800px]]
 +
 +
I have decomposed this assembly in three stage. For further informations, please read datasheets!
 +
*'''Stage 1 - Adaptation'''
 +
The purpose of this stage is to convert the FPGA's signals 3V3 in 5V signals. The transceiver 74LVXC3245 convert the bidirectionnal signals A0..A7 and the outputs ALE/AS, CS#, RD#/E and WR# from the FPGA.
 +
The connector P1 is connected to J20 on APF27-Dev.
 +
{{Note|The 3V3 voltage is supplied by the 39th pin of P1.}}
 +
*'''Stage 2 - CAN bus Controller'''
 +
The CAN bus controller receives messages from the adaptation stage (1). It is clocked with a 24Mhz Oscillator MXPO45HST24M0000. The SJA1000 send/receive message on/from the bus by communication with the TJA1040 on stage 3.
 +
{{Note| In our case, the interruption pin of the SJA1000 (INT#) is soldered on the switch S1 on the APF27-Dev but it is possible to through the FPGA!}}
 +
*'''Stage 3 - Communication with CAN bus'''
 +
The TJA1040 ensures the communication between the SJA1000 controller and the CAN bus. The split pin is used to stabilize the common mode and must be wired to GND.
 +
 +
== Pinout ==
 +
3V3 is supplied by pin 39 from J20 on APF27-Dev. This pin is wired to pin 1 for each 8-Bits transceivers.
 +
 +
'''Buffer U2 - address & data'''
 +
{| border="1" cellpadding="5" cellspacing="0" summary="J3 Pinout"
 +
|- style="background:#efefef;"
 +
! ''' J20 - Pins ''' || '''Name on APF27-Dev schematic''' || ''' Functionnalities '''
 +
|----------------
 +
| 13 || IO_L24P_3 || AD0
 +
|----------------
 +
| 14 || IO_L24N_3 || AD1
 +
|----------------
 +
| 15 || IO_L23P_3 || AD2
 +
|----------------
 +
| 16 || IO_L23N_3 || AD3
 +
|----------------
 +
| 17 || IO_L22P_3 || AD4
 +
|----------------
 +
| 18 || IO_L22N_3 || AD5
 +
|----------------
 +
| 19 || IO_L20P_3 || AD6
 +
|----------------
 +
| 20 || IO_L20N_3 || AD7
 +
|----------------
 +
|}
 +
 +
'''Buffer U1 - control'''
 +
{| border="1" cellpadding="5" cellspacing="0" summary="J3 Pinout"
 +
|- style="background:#efefef;"
 +
! ''' J20 - Pins ''' || '''Name on APF27-Dev schematic''' || ''' Functionnalities '''
 +
|----------------
 +
| 29 || IO_L08P_3 || ALE/AS
 +
|----------------
 +
| 31 || IO_L03P_3 || CS#
 +
|----------------
 +
| 32 || IO_L03N_3 || RD#/E
 +
|----------------
 +
| 33 || IO_L02P_3 || WR#
 +
|----------------
 +
|}
 +
 +
 +
== VHDL ==
 +
 +
Load the firmware in the FPGA of the ARMadeus Board
 +
 +
== Linux device platform source ==
 +
 +
Actually, the driver of the SJA1000 si present in the kernel, but the module can't be probed.
 +
First, you have to edit the makefile in ''buildroot/output/build/linux-2.6XXXX/drivers/net/can/sja1000/Makefile''.
 +
Replace the line
 +
<pre class="host">
 +
obj-$(CONFIG_CAN_SJA1000_PLATFORM) += sja1000_platform.o
 +
</pre>
 +
 +
By this one
 +
<pre class="host">
 +
obj-$(CONFIG_CAN_SJA1000_PLATFORM) += sja1000_platform.o sja1000_apf27dev.o
 +
</pre>
 +
 +
then, create the file sja1000_apf27dev.c and write your device module with the following structures :
 +
<source lang="c">
 +
static struct resource sja1000_resources[] = {
 +
[0] = {
 +
.start = ARMADEUS_FPGA_BASE_ADDR + SJA1000_WISHBONE_ADDRESS_BASE,
 +
.end = ARMADEUS_FPGA_BASE_ADDR + SJA1000_WISHBONE_ADDRESS_BASE + 0x1ff,
 +
.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
 +
},
 +
[1] = {
 +
.start = gpio_to_irq(IO_PIN_IRQ_SJA1000),
 +
.end    = gpio_to_irq(IO_PIN_IRQ_SJA1000),
 +
.flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 +
},
 +
};
 +
</source>
 +
 +
<source lang="c">
 +
static struct sja1000_platform_data sja1000_pdata = {
 +
.osc_freq = 24000000,
 +
.ocr = OCR_MODE_NORMAL | OCR_TX0_PULLDOWN | OCR_TX1_PULLDOWN,
 +
.cdr = CDR_PELICAN | CDR_CBP,
 +
};
 +
</source>
 +
 +
And reflash kernel and rootfs
 +
== Usage ==

Revision as of 19:36, 4 May 2011

This page explain how to communicate with a CAN bus through the SJA1000 CAN controller and a TJA1040 CAN Transceiver.

Warning Warning: There is no SJA1000 CAN controller on ARMadeus boards, you have to create your own assembly. The assembly used for doing this test is given on this page.


Page under construction... Construction.png Informations on this page are not guaranteed !!

Hardware Requirements

  • APF27-Dev and APF27 with FPGA Spartan 3A
  • 8 bits transceiver 74LVXC3245 (2x)
  • CAN bus controller SJA1000
  • 24Mhz oscillator MXO45HST24M0000
  • CAN bus transceiver TJA1040
  • Resistors and capacitances

Realisation

Foremost, you have to create the following assembly

Sja1000-APF27Dev-Mounting.png

I have decomposed this assembly in three stage. For further informations, please read datasheets!

  • Stage 1 - Adaptation

The purpose of this stage is to convert the FPGA's signals 3V3 in 5V signals. The transceiver 74LVXC3245 convert the bidirectionnal signals A0..A7 and the outputs ALE/AS, CS#, RD#/E and WR# from the FPGA. The connector P1 is connected to J20 on APF27-Dev.

Note Note: The 3V3 voltage is supplied by the 39th pin of P1.
  • Stage 2 - CAN bus Controller

The CAN bus controller receives messages from the adaptation stage (1). It is clocked with a 24Mhz Oscillator MXPO45HST24M0000. The SJA1000 send/receive message on/from the bus by communication with the TJA1040 on stage 3.

Note Note: In our case, the interruption pin of the SJA1000 (INT#) is soldered on the switch S1 on the APF27-Dev but it is possible to through the FPGA!
  • Stage 3 - Communication with CAN bus

The TJA1040 ensures the communication between the SJA1000 controller and the CAN bus. The split pin is used to stabilize the common mode and must be wired to GND.

Pinout

3V3 is supplied by pin 39 from J20 on APF27-Dev. This pin is wired to pin 1 for each 8-Bits transceivers.

Buffer U2 - address & data

J20 - Pins Name on APF27-Dev schematic Functionnalities
13 IO_L24P_3 AD0
14 IO_L24N_3 AD1
15 IO_L23P_3 AD2
16 IO_L23N_3 AD3
17 IO_L22P_3 AD4
18 IO_L22N_3 AD5
19 IO_L20P_3 AD6
20 IO_L20N_3 AD7

Buffer U1 - control

J20 - Pins Name on APF27-Dev schematic Functionnalities
29 IO_L08P_3 ALE/AS
31 IO_L03P_3 CS#
32 IO_L03N_3 RD#/E
33 IO_L02P_3 WR#


VHDL

Load the firmware in the FPGA of the ARMadeus Board

Linux device platform source

Actually, the driver of the SJA1000 si present in the kernel, but the module can't be probed. First, you have to edit the makefile in buildroot/output/build/linux-2.6XXXX/drivers/net/can/sja1000/Makefile. Replace the line 

obj-$(CONFIG_CAN_SJA1000_PLATFORM) += sja1000_platform.o

By this one 

obj-$(CONFIG_CAN_SJA1000_PLATFORM) += sja1000_platform.o sja1000_apf27dev.o

then, create the file sja1000_apf27dev.c and write your device module with the following structures : 

	static struct resource sja1000_resources[] = {
	[0] = {
		.start = ARMADEUS_FPGA_BASE_ADDR + SJA1000_WISHBONE_ADDRESS_BASE,
		.end = ARMADEUS_FPGA_BASE_ADDR + SJA1000_WISHBONE_ADDRESS_BASE + 0x1ff,
		.flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
	},
	[1] = {
		.start = gpio_to_irq(IO_PIN_IRQ_SJA1000),
		.end     = gpio_to_irq(IO_PIN_IRQ_SJA1000),
		.flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
	},
};

static struct sja1000_platform_data sja1000_pdata = {
	.osc_freq = 24000000,
	.ocr = OCR_MODE_NORMAL | OCR_TX0_PULLDOWN | OCR_TX1_PULLDOWN,
	.cdr = CDR_PELICAN | CDR_CBP,
};

And reflash kernel and rootfs

Usage

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