IMX9328-Spartan3 interface description

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Page under construction... Construction.png Informations on this page are not guaranteed !! This article describes the bus interface configuration to communicate between the i.MX9328 processor and the Spartan3 FPGA of the APF9328 board.

Default configuration on CS1n

CS1n is accessed via the address 0x1200 0000.


The clock used to clock the fpga is configured to 96 MHz.