Difference between revisions of "Qsys USB BLASTER Jtag-avalon-MM"
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[[Category: Quartus]] | [[Category: Quartus]] | ||
[[Category: USB-Blaster]] | [[Category: USB-Blaster]] | ||
| + | [[Category: APF6_SP]] | ||
| + | [[Category: CycloneV]] | ||
| + | [[Category: Qsys]] | ||
| + | |||
== Introduction == | == Introduction == | ||
| − | It's possible to access avalon-MM bus with an USB-Blaster connected to jtag. To do that a special ip-core must be instanciated in Qsys and a system console must be launched in Quartus. | + | It's possible to access avalon-MM bus with an [[Quartus_installation_on_Linux#USB-Blaster |USB-Blaster]] connected to jtag. To do that a special ip-core must be instanciated in Qsys and a system console must be launched in Quartus. |
== Instanciate Jtag-avalon-MM == | == Instanciate Jtag-avalon-MM == | ||
| + | In Qsys library, the component to instanciate is named '''JTAG to Avalon Master Bridge'''. | ||
| + | * Click twice on it to integrate it in your project then connect the clock and reset on the same signal than the avalon slave you want to access. | ||
| + | * Once done, plug the avalon interface «master» on the avalon slave interface you want to access. | ||
| + | * Generate the HDL files then synthesize all design. | ||
== Access avalon-MM registers == | == Access avalon-MM registers == | ||
| − | * Launch | + | * Launch System console in Quartus : |
<pre> | <pre> | ||
tools -> System debugging tools -> system console | tools -> System debugging tools -> system console | ||
| Line 18: | Line 26: | ||
* Connect to USB-BLaster JTAG-avalon-MM instance : | * Connect to USB-BLaster JTAG-avalon-MM instance : | ||
| − | < | + | <source lang="tcl"> |
% set masters [get_service_paths master] | % set masters [get_service_paths master] | ||
| + | /devices/5CGXBC3B(6|7)|5CGXFC3B(6|7)@1#1-1.2.4/(link)/JTAG/jtag_phy_1.jtag/phy_1/master | ||
% set master [lindex $masters 0] | % set master [lindex $masters 0] | ||
| + | /devices/5CGXBC3B(6|7)|5CGXFC3B(6|7)@1#1-1.2.4/(link)/JTAG/jtag_phy_1.jtag/phy_1/master | ||
% open_service master $master | % open_service master $master | ||
| − | </ | + | </source> |
* Write 32bits value | * Write 32bits value | ||
| − | < | + | <source lang="tcl"> |
% master_write_32 $master 0x4 0xdeadbeef | % master_write_32 $master 0x4 0xdeadbeef | ||
| − | </ | + | </source> |
* Read 32bits value | * Read 32bits value | ||
| − | < | + | <source lang="tcl"> |
% master_read_32 $master 0x0 2 | % master_read_32 $master 0x0 2 | ||
| − | </ | + | </source> |
| + | |||
| + | == Links == | ||
| + | |||
| + | * [https://www.altera.com/en_US/pdfs/literature/ug/ug_usb_blstr.pdf USB-Blaster (pdf)] | ||
| + | * [https://www.altera.com/en_US/pdfs/literature/hb/qts/qts_qii53028.pdf Analyzing and Debugging Designs with System Console] | ||
Latest revision as of 15:28, 23 August 2017
Introduction
It's possible to access avalon-MM bus with an USB-Blaster connected to jtag. To do that a special ip-core must be instanciated in Qsys and a system console must be launched in Quartus.
Instanciate Jtag-avalon-MM
In Qsys library, the component to instanciate is named JTAG to Avalon Master Bridge.
- Click twice on it to integrate it in your project then connect the clock and reset on the same signal than the avalon slave you want to access.
- Once done, plug the avalon interface «master» on the avalon slave interface you want to access.
- Generate the HDL files then synthesize all design.
Access avalon-MM registers
- Launch System console in Quartus :
tools -> System debugging tools -> system console
- Connect to USB-BLaster JTAG-avalon-MM instance :
% set masters [get_service_paths master]
/devices/5CGXBC3B(6|7)|5CGXFC3B(6|7)@1#1-1.2.4/(link)/JTAG/jtag_phy_1.jtag/phy_1/master
% set master [lindex $masters 0]
/devices/5CGXBC3B(6|7)|5CGXFC3B(6|7)@1#1-1.2.4/(link)/JTAG/jtag_phy_1.jtag/phy_1/master
% open_service master $master
- Write 32bits value
% master_write_32 $master 0x4 0xdeadbeef
- Read 32bits value
% master_read_32 $master 0x0 2
