Difference between revisions of "Using FPGA"

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(FPGA Interfaces)
(APF6_SP)
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* [[IMX51-Spartan6 interface description]]
 
* [[IMX51-Spartan6 interface description]]
 
==== [[APF6_SP]] ====
 
==== [[APF6_SP]] ====
 +
* [[APF6_SP_The_full_howto | The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]]
 
* [[IMX6-CycloneV interface description | IMX6-CycloneV interface description (PCIe)]]
 
* [[IMX6-CycloneV interface description | IMX6-CycloneV interface description (PCIe)]]
 
* [[DDR3-CycloneV interface description | DDR3-CycloneV interface description]]
 
* [[DDR3-CycloneV interface description | DDR3-CycloneV interface description]]

Revision as of 16:35, 2 February 2016


Developing on the APF FPGA

FPGA Interfaces

APF9328

APF27

APF51

APF6_SP


Using Armadeus FPGA

Manage the FPGA from Armadeus distribution.



Make some examples

These examples give the basis to make VHDL design for FPGA.



Design Tools

Description of tools used to simulate, to synthesize, and to download/configure FGPA.

Xilinx

Altera


Automatize FPGA design making

Peripherals On Demand

For complex projects, POD should be used to simplify design.

Migen

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

Chisel

With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis.

VHDL

Verilog

Links

Some useful links.

Wishbone

Spartan

CycloneV