Difference between revisions of "Using FPGA"
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Manage the FPGA from Armadeus distribution. | Manage the FPGA from Armadeus distribution. | ||
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* Configure the FPGA [[FPGA_loader | from Linux]], [[Target_Software_Installation#FPGA_firmware_test | from U-Boot]], [[PCIe_fpga_load | from PCIe]]. | * Configure the FPGA [[FPGA_loader | from Linux]], [[Target_Software_Installation#FPGA_firmware_test | from U-Boot]], [[PCIe_fpga_load | from PCIe]]. | ||
* Flashing FPGA firmware [[Uboot_FPGA_firmware_update_from_Linux | from Linux]], [[Target_Software_Installation#FPGA_firmware_installation | from U-Boot]] | * Flashing FPGA firmware [[Uboot_FPGA_firmware_update_from_Linux | from Linux]], [[Target_Software_Installation#FPGA_firmware_installation | from U-Boot]] | ||
* [[FPGA_register | Access the FPGA address domain from Linux]] | * [[FPGA_register | Access the FPGA address domain from Linux]] | ||
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=== Make some examples === | === Make some examples === | ||
Revision as of 16:41, 2 February 2016
Developing on the APF FPGA
FPGA InterfacesAPF9328APF27APF51APF6_SP
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Using Armadeus FPGAManage the FPGA from Armadeus distribution.
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Make some examplesThese examples give the basis to make VHDL design for FPGA.
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Design ToolsDescription of tools used to simulate, to synthesize, and to download/configure FGPA. Xilinx
Altera
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Automatize FPGA design makingPeripherals On DemandFor complex projects, POD should be used to simplify design. MigenWith migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis. ChiselWith Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis. |
VHDL
Verilog |
LinksSome useful links. Wishbone Spartan CycloneV |