Difference between revisions of "Using FPGA"

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=== Verilog ===
 
=== Verilog ===
  
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* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
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* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
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* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification
  
 
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Revision as of 07:57, 13 September 2018


Developing on the APF FPGA

FPGA Interfaces

Using Armadeus FPGA

Manage the FPGA from Armadeus distribution.

Make some examples

These examples give the basis to make VHDL design for FPGA.



Design Tools

Description of tools used to simulate, to synthesize, and to download/configure FGPA.

Xilinx

Altera

Lattice


Automatize FPGA design making

Peripherals On Demand

For complex projects, POD should be used to simplify design.

Migen

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

Chisel

With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis.

VHDL

Verilog

  • Verilator an High speed verilog simulator
  • Icarus Famous open-source verilog simulator
  • SymbiYosys open-source Verilog formal verification

Links

Some useful links.

Wishbone

Spartan

CycloneV