Difference between revisions of "Using FPGA"

From ArmadeusWiki
Jump to: navigation, search
m (→‎Designs)
(→‎Design Tools)
 
(88 intermediate revisions by 6 users not shown)
Line 1: Line 1:
 +
[[Category: FPGA]]
 
__NOTOC__
 
__NOTOC__
−
 
−
== First recommended readings ==
 
−
* [[FPGA | FPGA on APF introduction]]
 
  
 
==Developing on the APF FPGA==
 
==Developing on the APF FPGA==
  
−
{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionnalities" width="100%"
+
{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
 
|----------------
 
|----------------
 
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
 
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
  
 
| width="50%" |
 
| width="50%" |
−
=== Design Tools===
+
 
−
Description of tools used to simulate, to synthesize and to download/configure FGPA.
+
=== FPGA Interfaces ===
−
* [[Target_Software_Installation#FPGA_firmware_installation|FPGA firmware installation (on U-Boot)]]
+
 
−
* [[ISE WebPack installation on Linux| ISE WebPack (Xilinx's free devt tool) installation]]
+
* '''APF9328''': [[IMX9328-Spartan3 interface description]]
−
* [[How_to_make_a_VHDL_design_in_Ubuntu/Debian| How to setup the FPGA toolchain in Ubuntu/Debian]]
+
* '''APF27''': [[IMX27-Spartan3A interface description]]
−
* [[FPGA_loader | Configure the FPGA from Linux]]
+
* '''APF51''': [[IMX51-Spartan6 interface description]]
−
* [[FPGA_register | Access the FPGA address domain from Linux]]
+
* '''APF6_SP''': [[APF6_SP Interfaces description]]
−
* [[How to simulate post synthesis and post place & route design with GHDL]]
+
* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
  
 
| width="50%" |
 
| width="50%" |
  
−
===Xilinx documentation links===
+
===Using Armadeus FPGA===
−
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]
+
Manage the FPGA from Armadeus distribution.
 +
 
 +
* Configure the FPGA [[FPGA_loader | from Linux]], [[Target_Software_Installation#FPGA_firmware_test | from U-Boot]], [[PCIe_fpga_load | from PCIe]].
 +
* Flashing FPGA firmware [[Uboot_FPGA_firmware_update_from_Linux | from Linux]], [[Target_Software_Installation#FPGA_firmware_installation | from U-Boot]]
 +
* [[FPGA_register | Access the FPGA address domain from Linux]]
  
 
|----------------
 
|----------------
 
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
 
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
−
 
 
| width="50%" |
 
| width="50%" |
−
===Designs examples===
+
 
 +
=== Make some examples ===
 +
 
 +
These examples give the basis to make VHDL design for FPGA.
 +
 
 
* [[Simple blinking LED | LED]]
 
* [[Simple blinking LED | LED]]
−
* [[FPGA and led | Button and LED]]
+
* [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]
−
* [[A simple design with Wishbone bus | Button, Linux drivers, Wishbone bus communication and LED]]
+
 
 +
 
 +
 
  
 
| width="50%" |
 
| width="50%" |
  
−
===VHDL ===
+
=== Design Tools===
 +
Description of tools used to simulate, to synthesize, and to download/configure FGPA.
  
−
* [[VHDL coding styles]]
+
'''Xilinx'''
−
* [http://www.xess.com/ho03000.html Nice ideas/examples to look at]
+
* [[ISE WebPack and Vivado]]
−
* [http://www.opencores.org www.opencores.org]
+
 
−
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]
+
'''Altera'''
 +
* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
 +
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]
 +
 
 +
'''Lattice'''
 +
 
 +
* [[IceCube | Install IceCube]]
 +
* [[Diamond | Install Lattice Diamond]]
 +
 
 +
'''Microsemi'''
 +
* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]
  
 
|----------------
 
|----------------
Line 48: Line 66:
 
| width="50%" |
 
| width="50%" |
  
−
==='''P'''eripheral '''O'''n '''D'''emand ===
+
=== Automatize FPGA design making ===
  
−
POD is a Python tool that allows you to easily create FPGA bitfiles for your
+
==== [[Peripherals On Demand]] ====
−
embedded system, from several Open Source IPs (compatibles with the OpenCores
+
For complex projects, POD should be used to simplify design.
−
Wishbone bus). It will also generates the corresponding drivers (currently only
+
 
−
Linux ones).  
+
==== [[FuseSoC]] ====
 +
FuseSoC is a builder written in Python used to automatize FPGA constructions
 +
 
 +
==== CactusII ====
 +
 
 +
[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.
  
−
* [[POD specification]]
 
−
* [https://sourceforge.net/projects/periphondemand/ sources repository]
 
 
| width="50%" |
 
| width="50%" |
−
===Links Wishbone===
+
 
−
* [http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf  official Wishbone specifications]
+
=== HDL ===
−
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]
+
 
 +
===VHDL ===
 +
 
 +
* [[VHDL coding styles|VHDL coding styles & externals documentations]]
 +
* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
 +
* [http://www.opencores.org www.opencores.org]
 +
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]
 +
 
 +
=== Verilog ===
 +
 
 +
* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
 +
* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
 +
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification
 +
 
 +
=== Synthesizable Synchronous HDL ===
 +
==== [[Migen]] ====
 +
 
 +
With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.
 +
 
 +
==== [[Chisel]] ====
 +
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.
 +
 
 +
==== [[SpinalHDL]] ====
 +
 
 +
[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.
  
 
|----------------
 
|----------------
Line 67: Line 112:
 
| width="50%" |
 
| width="50%" |
  
−
Orchestra is a tools similar to POD developed by one member of ARMadeus Project:
+
===Links===
−
* [[Orchestra | Spécification d'Orchestra (French)]]
+
Some useful links.
  
 +
''' Wishbone '''
 +
* [http://cdn.opencores.org/downloads/wbspec_b3.pdf  official Wishbone specifications]
 +
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]
 +
 +
''' Spartan '''
 +
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]
 +
 +
''' CycloneV'''
 +
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]
 +
 +
''' OpenSource '''
 +
 +
* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]
 +
 +
| width="50%" |
  
−
|----------------
 
  
  
 
|}
 
|}

Latest revision as of 14:45, 12 November 2019


Developing on the APF FPGA

FPGA Interfaces

Using Armadeus FPGA

Manage the FPGA from Armadeus distribution.

Make some examples

These examples give the basis to make VHDL design for FPGA.



Design Tools

Description of tools used to simulate, to synthesize, and to download/configure FGPA.

Xilinx

Altera

Lattice

Microsemi

Automatize FPGA design making

Peripherals On Demand

For complex projects, POD should be used to simplify design.

FuseSoC

FuseSoC is a builder written in Python used to automatize FPGA constructions

CactusII

Graphical IDE for managing FPGA/ASIC design with IPX-ACT standard.

HDL

VHDL

Verilog

  • Verilator an High speed verilog simulator
  • Icarus Famous open-source verilog simulator
  • SymbiYosys open-source Verilog formal verification

Synthesizable Synchronous HDL

Migen

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

Chisel

With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

SpinalHDL

Another HDL generator (VHDL) written in Scala.

Links

Some useful links.

Wishbone

Spartan

CycloneV

OpenSource


Retrieved from "http://www.armadeus.org/wiki/index.php?title=Using_FPGA&oldid=14851"