Difference between revisions of "Using FPGA"
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+ | [[Category: FPGA]] | ||
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==Developing on the APF FPGA== | ==Developing on the APF FPGA== | ||
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− | * [[ | + | === FPGA Interfaces === |
− | * [[ | + | |
− | * [[ | + | * '''APF9328''': [[IMX9328-Spartan3 interface description]] |
+ | * '''APF27''': [[IMX27-Spartan3A interface description]] | ||
+ | * '''APF51''': [[IMX51-Spartan6 interface description]] | ||
+ | * '''APF6_SP''': [[APF6_SP Interfaces description]] | ||
+ | * '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]] | ||
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− | ===Using | + | ===Using Armadeus FPGA=== |
− | Manage the | + | Manage the FPGA from Armadeus distribution. |
− | * [[FPGA_loader | | + | * Configure the FPGA [[FPGA_loader | from Linux]], [[Target_Software_Installation#FPGA_firmware_test | from U-Boot]], [[PCIe_fpga_load | from PCIe]]. |
− | * [[Target_Software_Installation#FPGA_firmware_installation| | + | * Flashing FPGA firmware [[Uboot_FPGA_firmware_update_from_Linux | from Linux]], [[Target_Software_Installation#FPGA_firmware_installation | from U-Boot]] |
* [[FPGA_register | Access the FPGA address domain from Linux]] | * [[FPGA_register | Access the FPGA address domain from Linux]] | ||
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| width="50%" | | | width="50%" | | ||
− | === | + | === Make some examples === |
These examples give the basis to make VHDL design for FPGA. | These examples give the basis to make VHDL design for FPGA. | ||
* [[Simple blinking LED | LED]] | * [[Simple blinking LED | LED]] | ||
− | + | * [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]] | |
− | * [[A simple design with Wishbone bus | | + | |
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+ | | width="50%" | | ||
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+ | === Design Tools=== | ||
+ | Description of tools used to simulate, to synthesize, and to download/configure FGPA. | ||
+ | |||
+ | '''Xilinx''' | ||
+ | * [[ISE WebPack and Vivado]] | ||
+ | |||
+ | '''Altera''' | ||
+ | * [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]] | ||
+ | * [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]] | ||
+ | |||
+ | '''Lattice''' | ||
+ | |||
+ | * [[IceCube | Install IceCube]] | ||
+ | * [[Diamond | Install Lattice Diamond]] | ||
+ | |||
+ | '''Microsemi''' | ||
+ | * [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero] | ||
+ | |||
+ | |---------------- | ||
+ | |- style="background:#f4f4f4; color:black; -moz-border-radius:18px;" | ||
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+ | | width="50%" | | ||
+ | |||
+ | === Automatize FPGA design making === | ||
+ | |||
+ | ==== [[Peripherals On Demand]] ==== | ||
For complex projects, POD should be used to simplify design. | For complex projects, POD should be used to simplify design. | ||
+ | |||
+ | ==== [[FuseSoC]] ==== | ||
+ | FuseSoC is a builder written in Python used to automatize FPGA constructions | ||
+ | |||
+ | ==== CactusII ==== | ||
+ | |||
+ | [http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard. | ||
| width="50%" | | | width="50%" | | ||
+ | |||
+ | === HDL === | ||
===VHDL === | ===VHDL === | ||
− | * [[VHDL coding styles]] | + | * [[VHDL coding styles|VHDL coding styles & externals documentations]] |
− | * [http://www.xess.com/ | + | * [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at] |
* [http://www.opencores.org www.opencores.org] | * [http://www.opencores.org www.opencores.org] | ||
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial] | * [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial] | ||
− | + | === Verilog === | |
− | + | ||
− | + | * [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator | |
+ | * [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator | ||
+ | * [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification | ||
− | ===[[ | + | === Synthesizable Synchronous HDL === |
+ | ==== [[Migen]] ==== | ||
+ | With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis. | ||
+ | ==== [[Chisel]] ==== | ||
+ | With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board. | ||
+ | |||
+ | ==== [[SpinalHDL]] ==== | ||
+ | |||
+ | [https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala. | ||
+ | |||
+ | |---------------- | ||
+ | |- style="background:#f4f4f4; color:black; -moz-border-radius:18px;" | ||
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''' Wishbone ''' | ''' Wishbone ''' | ||
− | * [http:// | + | * [http://cdn.opencores.org/downloads/wbspec_b3.pdf official Wishbone specifications] |
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc] | * [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc] | ||
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* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet] | * [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet] | ||
− | ''' | + | ''' CycloneV''' |
− | * [ | + | * [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera] |
− | * [http:// | + | |
+ | ''' OpenSource ''' | ||
+ | |||
+ | * [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map] | ||
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+ | | width="50%" | | ||
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|} | |} |
Latest revision as of 14:45, 12 November 2019
Developing on the APF FPGA
FPGA Interfaces
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Using Armadeus FPGAManage the FPGA from Armadeus distribution.
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Make some examplesThese examples give the basis to make VHDL design for FPGA.
|
Design ToolsDescription of tools used to simulate, to synthesize, and to download/configure FGPA. Xilinx Altera Lattice Microsemi |
Automatize FPGA design makingPeripherals On DemandFor complex projects, POD should be used to simplify design. FuseSoCFuseSoC is a builder written in Python used to automatize FPGA constructions CactusIIGraphical IDE for managing FPGA/ASIC design with IPX-ACT standard. |
HDLVHDL
Verilog
Synthesizable Synchronous HDLMigenWith migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis. ChiselWith Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board. SpinalHDLAnother HDL generator (VHDL) written in Scala. |
LinksSome useful links. Wishbone Spartan CycloneV OpenSource |
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