Difference between revisions of "Using FPGA"
From ArmadeusWiki
(→FPGA Interfaces) |
(→Design Tools) |
||
(13 intermediate revisions by the same user not shown) | |||
Line 12: | Line 12: | ||
=== FPGA Interfaces === | === FPGA Interfaces === | ||
− | + | * '''APF9328''': [[IMX9328-Spartan3 interface description]] | |
− | + | * '''APF27''': [[IMX27-Spartan3A interface description]] | |
− | + | * '''APF51''': [[IMX51-Spartan6 interface description]] | |
− | + | * '''APF6_SP''': [[APF6_SP Interfaces description]] | |
− | + | * '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]] | |
− | + | ||
− | + | ||
− | + | ||
− | * [[ | + | |
− | + | ||
− | + | ||
| width="50%" | | | width="50%" | | ||
Line 29: | Line 23: | ||
Manage the FPGA from Armadeus distribution. | Manage the FPGA from Armadeus distribution. | ||
− | |||
* Configure the FPGA [[FPGA_loader | from Linux]], [[Target_Software_Installation#FPGA_firmware_test | from U-Boot]], [[PCIe_fpga_load | from PCIe]]. | * Configure the FPGA [[FPGA_loader | from Linux]], [[Target_Software_Installation#FPGA_firmware_test | from U-Boot]], [[PCIe_fpga_load | from PCIe]]. | ||
* Flashing FPGA firmware [[Uboot_FPGA_firmware_update_from_Linux | from Linux]], [[Target_Software_Installation#FPGA_firmware_installation | from U-Boot]] | * Flashing FPGA firmware [[Uboot_FPGA_firmware_update_from_Linux | from Linux]], [[Target_Software_Installation#FPGA_firmware_installation | from U-Boot]] | ||
* [[FPGA_register | Access the FPGA address domain from Linux]] | * [[FPGA_register | Access the FPGA address domain from Linux]] | ||
− | |||
− | |||
− | |||
|---------------- | |---------------- | ||
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;" | |- style="background:#f4f4f4; color:black; -moz-border-radius:18px;" | ||
| width="50%" | | | width="50%" | | ||
+ | |||
=== Make some examples === | === Make some examples === | ||
Line 56: | Line 47: | ||
'''Xilinx''' | '''Xilinx''' | ||
− | * [[ISE WebPack | + | * [[ISE WebPack and Vivado]] |
− | + | ||
− | + | ||
− | + | ||
'''Altera''' | '''Altera''' | ||
* [[Quartus | Quartus Web edition (Altera's free devt tool)]] | * [[Quartus | Quartus Web edition (Altera's free devt tool)]] | ||
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]] | * [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]] | ||
+ | '''Lattice''' | ||
+ | |||
+ | * [[IceCube | Install IceCube]] | ||
+ | * [[Diamond | Install Lattice Diamond]] | ||
+ | |||
+ | '''Microsemi''' | ||
+ | * [[Libero | Install Libero]] | ||
|---------------- | |---------------- | ||
Line 75: | Line 71: | ||
For complex projects, POD should be used to simplify design. | For complex projects, POD should be used to simplify design. | ||
− | |||
− | |||
− | |||
− | |||
− | |||
| width="50%" | | | width="50%" | | ||
+ | |||
+ | === HDL === | ||
===VHDL === | ===VHDL === | ||
Line 93: | Line 86: | ||
=== Verilog === | === Verilog === | ||
+ | * [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator | ||
+ | * [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator | ||
+ | * [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification | ||
+ | |||
+ | === Synthesizable Synchronous HDL === | ||
+ | ==== [[Migen]] ==== | ||
+ | |||
+ | With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis. | ||
+ | |||
+ | ==== [[Chisel]] ==== | ||
+ | With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis. Armadeus system can help you to integrate a Chisel project on Armadeus board. | ||
|---------------- | |---------------- | ||
Line 111: | Line 115: | ||
''' CycloneV''' | ''' CycloneV''' | ||
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera] | * [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera] | ||
+ | |||
+ | ''' OpenSource ''' | ||
+ | |||
+ | * [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map] | ||
+ | |||
| width="50%" | | | width="50%" | | ||
+ | |||
+ | |||
+ | |||
|} | |} |
Revision as of 15:41, 30 October 2018
Developing on the APF FPGA
FPGA Interfaces
|
Using Armadeus FPGAManage the FPGA from Armadeus distribution.
|
Make some examplesThese examples give the basis to make VHDL design for FPGA.
|
Design ToolsDescription of tools used to simulate, to synthesize, and to download/configure FGPA. Xilinx Altera Lattice Microsemi |
Automatize FPGA design makingPeripherals On DemandFor complex projects, POD should be used to simplify design.
|
HDLVHDL
Verilog
Synthesizable Synchronous HDLMigenWith migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis. ChiselWith Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis. Armadeus system can help you to integrate a Chisel project on Armadeus board. |
LinksSome useful links. Wishbone Spartan CycloneV OpenSource |
|