Developing on the APF FPGA
Using Armadeus FPGA
Manage the FPGA from Armadeus distribution.
Make some examples
These examples give the basis to make VHDL design for FPGA.
Description of tools used to simulate, to synthesize, and to download/configure FGPA.
Automatize FPGA design making
Peripherals On Demand
For complex projects, POD should be used to simplify design.
FuseSoC is a builder written in Python used to automatize FPGA constructions
Graphical IDE for managing FPGA/ASIC design with IPX-ACT standard.
Synthesizable Synchronous HDL
With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.
Another HDL generator (VHDL) written in Scala.
Some useful links.